[PATCH] D146950: [Xtensa] Implement load pseudo operations and patterns.
Andrei Safronov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 27 05:34:38 PDT 2023
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Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D146950
Files:
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
Index: llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
+++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -107,6 +107,7 @@
bool Valid = false;
switch (MI.getOpcode()) {
+ case Xtensa::L8I_P:
case Xtensa::L8UI:
case Xtensa::S8I:
Valid = (Offset >= 0 && Offset <= 255);
Index: llvm/lib/Target/Xtensa/XtensaInstrInfo.td
===================================================================
--- llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -284,6 +284,18 @@
}
}
+// Xtensa missed L8I load operation, use pseudo operation
+let usesCustomInserter = 1 in
+def L8I_P: Pseudo<(outs AR:$t), (ins mem8:$addr),
+ "!L8I_P $t, $addr",
+ [(set AR:$t, (sextloadi8
+ addr_ish1:$addr))]>;
+
+//extending loads
+def : Pat<(i32 (extloadi1 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+def : Pat<(i32 (extloadi8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+def : Pat<(i32 (extloadi16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
+
//===----------------------------------------------------------------------===//
// Conditional branch instructions
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
===================================================================
--- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -1099,6 +1099,8 @@
MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
MachineInstr &MI, MachineBasicBlock *MBB) const {
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+ MachineFunction *MF = MBB->getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
switch (MI.getOpcode()) {
@@ -1136,6 +1138,24 @@
return MBB;
}
+ case Xtensa::L8I_P: {
+ MachineOperand &R = MI.getOperand(0);
+ MachineOperand &Op1 = MI.getOperand(1);
+ MachineOperand &Op2 = MI.getOperand(2);
+
+ const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+ unsigned R1 = MRI.createVirtualRegister(RC);
+
+ BuildMI(*MBB, MI, DL, TII.get(Xtensa::L8UI), R1).add(Op1).add(Op2);
+
+ unsigned R2 = MRI.createVirtualRegister(RC);
+ BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLLI), R2).addReg(R1).addImm(24);
+ BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRAI), R.getReg())
+ .addReg(R2)
+ .addImm(24);
+ MI.eraseFromParent();
+ return MBB;
+ }
default:
llvm_unreachable("Unexpected instr type to insert");
}
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