[PATCH] D145583: [AArch64][SME] Fix an infinite loop in DAGCombine related to adding -force-streaming-compatible-sve flag.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll:932
+  %5 = insertelement <8 x i64> poison, i64 %4, i64 0
+  %6 = shufflevector <8 x i64> %5, <8 x i64> zeroinitializer, <8 x i32> zeroinitializer
+  %7 = mul <8 x i64> %6, %1
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This could be `poison` as well.


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Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll:934-935
+  %7 = mul <8 x i64> %6, %1
+  %.not = icmp sgt <8 x i64> %7, poison
+  %8 = zext <8 x i1> %.not to <8 x i16>
+  store <8 x i16> %8, ptr %2, align 2
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I'm not sure why the `icmp` and `zext` are relevant to this test.


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Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll:953
+  %2 = add <8 x i32> %1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  store <8 x i32> %2, ptr %s, align 2
+  ret void
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Can you just store `%1` directly without the add?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145583/new/

https://reviews.llvm.org/D145583