[PATCH] D146488: [RISCV] Move compressible registers to the beginning of the FP allocation order.

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

I can't say I've done any real performance analysis, but this seems sensible to me and I didn't spot any obvious regressions from kicking the tires.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D146488/new/

https://reviews.llvm.org/D146488