[PATCH] D146930: [MCP] Properly handle sub-register forwarding

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 updated this revision to Diff 508494.
barannikov88 added a comment.

Strip changes that are not necessary for fixing the bug.
They will be in a separate commit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146930/new/

https://reviews.llvm.org/D146930

Files:
  llvm/lib/CodeGen/MachineCopyPropagation.cpp
  llvm/test/CodeGen/ARM/pr60908.mir


Index: llvm/test/CodeGen/ARM/pr60908.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/pr60908.mir
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=armv7 -run-pass=machine-cp %s -o - | FileCheck %s
+
+# Positive test: $d15 has sub-register $s30, which should be propagated.
+---
+name:            test_d15
+tracksRegLiveness: true
+liveins:
+  - { reg: '$d15' }
+body:             |
+  bb.0.entry:
+    liveins: $d15
+
+    ; CHECK-LABEL: name: test_d15
+    ; CHECK: liveins: $d15
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: renamable $s0 = COPY $s30
+    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
+    renamable $d14 = COPY killed renamable $d15
+    renamable $s0 = COPY killed renamable $s28
+    BX_RET 14 /* CC::al */, $noreg, implicit $s0
+
+...
+
+# Negative test: $d18 does not have sub-registers.
+---
+name:            test_d18
+tracksRegLiveness: true
+liveins:
+  - { reg: '$d18' }
+body:             |
+  bb.0.entry:
+    liveins: $d18
+
+    ; CHECK-LABEL: name: test_d18
+    ; CHECK: liveins: $d18
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: renamable $d14 = COPY killed renamable $d18
+    ; CHECK-NEXT: renamable $s0 = COPY killed renamable $s28
+    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
+    renamable $d14 = COPY killed renamable $d18
+    renamable $s0 = COPY killed renamable $s28
+    BX_RET 14 /* CC::al */, $noreg, implicit $s0
+
+...
Index: llvm/lib/CodeGen/MachineCopyPropagation.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -643,15 +643,18 @@
     const MachineOperand &CopySrc = *CopyOperands->Source;
     Register CopySrcReg = CopySrc.getReg();
 
-    // When the use is a subregister of the COPY destination,
-    // record the subreg index.
-    unsigned SubregIdx = 0;
-
-    // This can only occur when we are dealing with physical registers.
+    Register ForwardedReg = CopySrcReg;
+    // MI might use a sub-register of the Copy destination, in which case the
+    // forwarded register is the matching sub-register of the Copy source.
     if (MOUse.getReg() != CopyDstReg) {
-      SubregIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg());
-      if (!SubregIdx)
+      unsigned SubRegIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg());
+      assert(SubRegIdx && "findAvailCopy returned unrelated instruction");
+      ForwardedReg = TRI->getSubReg(CopySrcReg, SubRegIdx);
+      if (!ForwardedReg) {
+        LLVM_DEBUG(dbgs() << "MCP: Copy source does not have sub-register "
+                          << TRI->getSubRegIndexName(SubRegIdx) << '\n');
         continue;
+      }
     }
 
     // Don't forward COPYs of reserved regs unless they are constant.
@@ -681,13 +684,10 @@
     }
 
     LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
-                      << "\n     with " << printReg(CopySrcReg, TRI)
+                      << "\n     with " << printReg(ForwardedReg, TRI)
                       << "\n     in " << MI << "     from " << *Copy);
 
-    if (SubregIdx)
-      MOUse.setReg(TRI->getSubReg(CopySrcReg, SubregIdx));
-    else
-      MOUse.setReg(CopySrcReg);
+    MOUse.setReg(ForwardedReg);
 
     if (!CopySrc.isRenamable())
       MOUse.setIsRenamable(false);


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