[llvm] 62c38ff - [Target] Use isNullConstant (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 26 23:34:27 PDT 2023
Author: Kazu Hirata
Date: 2023-03-26T23:34:13-07:00
New Revision: 62c38ffb15fac7c82dee83002ffd9267553fb534
URL: https://github.com/llvm/llvm-project/commit/62c38ffb15fac7c82dee83002ffd9267553fb534
DIFF: https://github.com/llvm/llvm-project/commit/62c38ffb15fac7c82dee83002ffd9267553fb534.diff
LOG: [Target] Use isNullConstant (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0612304fb8fa3..521caad76932f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16586,7 +16586,6 @@ performExtractVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
SelectionDAG &DAG = DCI.DAG;
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
- ConstantSDNode *ConstantN1 = dyn_cast<ConstantSDNode>(N1);
EVT VT = N->getValueType(0);
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
@@ -16605,8 +16604,7 @@ performExtractVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
// (extract_vector_elt (vXf32 Other) 1))
// For strict_fadd we need to make sure the old strict_fadd can be deleted, so
// we can only do this when it's used only by the extract_vector_elt.
- if (ConstantN1 && ConstantN1->getZExtValue() == 0 &&
- hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) &&
+ if (isNullConstant(N1) && hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) &&
(!IsStrict || N0.hasOneUse())) {
SDLoc DL(N0);
SDValue N00 = N0->getOperand(IsStrict ? 1 : 0);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index d71ea740d3fb1..e3f581ef0f74f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7246,10 +7246,8 @@ SDValue SITargetLowering::lowerRawBufferAtomicIntrin(SDValue Op,
// Return a value to use for the idxen operand by examining the vindex operand.
static unsigned getIdxEn(SDValue VIndex) {
- if (auto VIndexC = dyn_cast<ConstantSDNode>(VIndex))
- // No need to set idxen if vindex is known to be zero.
- return VIndexC->getZExtValue() != 0;
- return 1;
+ // No need to set idxen if vindex is known to be zero.
+ return isNullConstant(VIndex) ? 0 : 1;
}
SDValue
@@ -11287,8 +11285,8 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
}
case ISD::ADDCARRY: {
// add x, (addcarry y, 0, cc) => addcarry x, y, cc
- auto C = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
- if (!C || C->getZExtValue() != 0) break;
+ if (!isNullConstant(RHS.getOperand(1)))
+ break;
SDValue Args[] = { LHS, RHS.getOperand(0), RHS.getOperand(2) };
return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args);
}
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