[PATCH] D146933: [RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec

[Alex Bradbury via Phabricator via llvm-commits]

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Table A.6 in the RISC-V ISA Manual indicates that sequentially consistent atomic ops that have a matching instruction should be mapped to `amo<op>.{w|d}.aqrl`. But sequentially consistent operations that are mapped to lr/sc should produce `loop: lr.{w|d}.aqrl; <op>; sc.{w|d}.rl; bnez loop`. Previously, LLVM produced an `sc.{w|d}.aqrl` which was stronger than necessary. This patch adjusts the relevant logic so that a `sc.{w|d}.rl` is produced.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146933

Files:
  llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
  llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

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