[PATCH] D146930: [MCP] Properly handle sub-register forwarding

[Sergei Barannikov via Phabricator via llvm-commits]

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1. In this example:

  $d14 = COPY killed $d18
  $s0 = MI $s28

$s28 is a sub-register of $d14. However, $d18 does not have
sub-registers and thus cannot be forwarded. Previously, this resulted
in $noreg being substituted in place of the use of $s28, which later
led to an assertion failure.

2. `isForwardableRegClassCopy` was updated to take into accout the

possibility of forwarding a sub-register of the original copy source.
Previously, it disallowed otherwise legal transformation if the user
of the COPY was not itself a COPY.

3. mcp-overlap-after-propagation.mir was updated because it hasn't been

catching the bug since D67794 <https://reviews.llvm.org/D67794>.

Fixes https://github.com/llvm/llvm-project/issues/60908, a regression
that was introduced in D141747 <https://reviews.llvm.org/D141747>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146930

Files:
  llvm/lib/CodeGen/MachineCopyPropagation.cpp
  llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll
  llvm/test/CodeGen/AArch64/swifterror.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
  llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
  llvm/test/CodeGen/ARM/bf16-shuffle.ll
  llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
  llvm/test/CodeGen/ARM/pr60908.mir
  llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
  llvm/test/CodeGen/Hexagon/swp-reuse-phi-6.ll
  llvm/test/CodeGen/PowerPC/fp-strict-round.ll
  llvm/test/CodeGen/PowerPC/frem.ll
  llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
  llvm/test/CodeGen/PowerPC/ldst-16-byte.mir
  llvm/test/CodeGen/PowerPC/machine-pre.ll
  llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
  llvm/test/CodeGen/PowerPC/tail-dup-break-cfg.ll
  llvm/test/CodeGen/PowerPC/tail-dup-layout.ll
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-mul.ll
  llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-i64-add.ll
  llvm/test/CodeGen/Thumb2/mve-div-expand.ll
  llvm/test/CodeGen/Thumb2/mve-fmath.ll
  llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
  llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-frint.ll
  llvm/test/CodeGen/Thumb2/mve-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-nofloat.ll
  llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
  llvm/test/CodeGen/Thumb2/mve-vabd.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
  llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
  llvm/test/CodeGen/X86/AMX/amx-across-func.ll
  llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
  llvm/test/CodeGen/X86/abds.ll
  llvm/test/CodeGen/X86/abdu.ll
  llvm/test/CodeGen/X86/abs.ll
  llvm/test/CodeGen/X86/add-and-not.ll
  llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll
  llvm/test/CodeGen/X86/cgp-usubo.ll
  llvm/test/CodeGen/X86/combine-srem.ll
  llvm/test/CodeGen/X86/extract-bits.ll
  llvm/test/CodeGen/X86/fast-isel-store.ll
  llvm/test/CodeGen/X86/freeze.ll
  llvm/test/CodeGen/X86/funnel-shift.ll
  llvm/test/CodeGen/X86/iabs.ll
  llvm/test/CodeGen/X86/midpoint-int.ll
  llvm/test/CodeGen/X86/peep-setb.ll
  llvm/test/CodeGen/X86/signbit-test.ll
  llvm/test/CodeGen/X86/smax.ll
  llvm/test/CodeGen/X86/smin.ll
  llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll
  llvm/test/CodeGen/X86/swift-return.ll
  llvm/test/CodeGen/X86/umax.ll
  llvm/test/CodeGen/X86/umin.ll
  llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll

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