[PATCH] D146787: [X86] Teach computeKnownBitsForTargetNode about MUL_IMM

[Kazu Hirata via Phabricator via llvm-commits]

kazu added inline comments.


================
Comment at: llvm/test/CodeGen/X86/select-constant-lea.ll:20
 ; SLOWLEA3-NEXT:    leal (%rax,%rax,4), %eax
-; SLOWLEA3-NEXT:    orl $8, %eax
+; SLOWLEA3-NEXT:    addl $8, %eax
 ; SLOWLEA3-NEXT:    retq
----------------
RKSimon wrote:
> Please can you confirm what's caused us to use the ORLIke pattern?
`combineSelectOfTwoConstants` expands `ISD::SELECT` as:

```
    // select Cond, TC, FC --> (zext(Cond) * (TC - FC)) + FC                                        
```

with `ISD::ADD`.  Then `DAGCombiner::visitADD` does:

```
  // fold (a+b) -> (a|b) iff a and b share no bits.                                                 
  if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
      DAG.haveNoCommonBitsSet(N0, N1))
    return DAG.getNode(ISD::OR, DL, VT, N0, N1);
```

This is where the `ISD::OR` comes from.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D146787/new/

https://reviews.llvm.org/D146787