[PATCH] D146121: [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits (WIP)

Sun Mar 26 17:59:11 PDT 2023

pengfei added inline comments.

================
Comment at: llvm/test/CodeGen/X86/h-register-addressing-64.ll:67
+; CHECK-NEXT:    andl $2040, %esi # imm = 0x7F8
+; CHECK-NEXT:    movzbl (%rdi,%rsi), %eax
 ; CHECK-NEXT:    retq
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goldstein.w.n wrote:
> RKSimon wrote:
> > kazu wrote:
> > > goldstein.w.n wrote:
> > > > I think this is okay here. We only get the right codegen by chance here and I don't think its something we can reasonably control during DAG isel.
> > > > 
> > > > I tried to improve this with D141653. Looked good for the tests but caused infinite loop in bootstrap build.
> > > > 
> > > > I think this (along with other `imm` level optimizations), need to be moved to a new pass (or function in isel) that runs at the very end.
> > > > > think this (along with other `imm` level optimizations), need to be moved to a new pass (or function in isel) that runs at the very end.
> > > 
> > > I was just thinking about something similar.  Specifically, optimizations to achieve smaller encoding with the same opcode should move to a new pass.  Otherwise, we would have to see through `ISD::ZERO_EXTEND` and `ISD::TRUNCATE` everywhere, and that would be prone to missed optimizations.
> > > 
> > > Do we have known bits and demanded bits infrastructure at the x86 MIR level?  (I'm guessing not.)  Also, I am wondering whether a new pass would be more effective if we use information across basic blocks.
> > Adding value tracking at that level would be a huge amount of work - both X86 and AMDGPU currently using the DAG narrowing code, but ideally we'd be working to enable it on other targets as well.
> I was thinking it would be best saved for a pass between DAG narrowing and MIR. I.e DAG narrowing -> Imm Fixup -> MIR. Imm Fixup could work on SDValue types.
Any possibility it can be solved in a new ISel mechanism like GlobalISel?

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  https://reviews.llvm.org/D146121/new/

https://reviews.llvm.org/D146121