[PATCH] D146789: [LegalizeTypes][TargetLowering][RISCV] Fix regressions from D146786.

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/overflow-intrinsics.ll:663
 
 define i1 @uaddo_i64_decrement_alt(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt:
----------------
RV32 and RV64 each add an mv(COPY) instruction, the instruction is added by virtregrewriter.

But the whole is good, maybe we can add a todo, lest we forget.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146789/new/

https://reviews.llvm.org/D146789