[PATCH] D145085: [RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:14971
+  if (Fractional)
+    return Factor / LMUL <= 8;
+  return Factor * LMUL <= 8;
----------------
You can return `true` for Fractional. This division can only produce 1 or 0. Factor is 2-8 and LMUL is 2, 4, or 8.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:15062
+  auto Mask = SVI->getShuffleMask();
+  SmallVector<Value *, 8> Ops;
+
----------------
8->10 to over the maximum operands: 8 vectors + pointer + VL


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:289
+
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVCodeGenPreparePass());
----------------
Merge these 3 ifs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145085/new/

https://reviews.llvm.org/D145085