[llvm] 08be5e2 - [RISCV][NFC] Added possible SEWs associated with a given LMUL

[Nitin John Raj via llvm-commits]

Author: Nitin John Raj
Date: 2023-03-24T16:33:24-07:00
New Revision: 08be5e25376dff9a5db34cd583ff82c2b7a8b4d2

URL: https://github.com/llvm/llvm-project/commit/08be5e25376dff9a5db34cd583ff82c2b7a8b4d2
DIFF: https://github.com/llvm/llvm-project/commit/08be5e25376dff9a5db34cd583ff82c2b7a8b4d2.diff

LOG: [RISCV][NFC] Added possible SEWs associated with a given LMUL

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVScheduleV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 0f856086fee0..61a755d08582 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -17,10 +17,19 @@ defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = !listremove(SchedMxList, ["MF8"]);
 
+class SchedSEWSet<string mx> {
+  list<int> val = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
+                        !eq(mx, "M2"):  [8, 16, 32, 64],
+                        !eq(mx, "M4"):  [8, 16, 32, 64],
+                        !eq(mx, "M8"):  [8, 16, 32, 64],
+                        !eq(mx, "MF2"): [8, 16, 32],
+                        !eq(mx, "MF4"): [8, 16],
+                        !eq(mx, "MF8"): [8]);
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair for each LMUL in each of the
 // SchedMxList variants above.
-
 multiclass LMULSchedWritesImpl<string name, list<string> MxList> {
   foreach mx = MxList in {
     def name # "_" # mx : SchedWrite;