[llvm] 51e5846 - [RISCV][NFC] Renamed [Read/Write]VGather* -> [Read/Write]VRGatherV*
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 24 16:40:58 PDT 2023
Author: Nitin John Raj
Date: 2023-03-24T16:33:23-07:00
New Revision: 51e5846b5645f4a7f6065df1cebaf2842222c180
URL: https://github.com/llvm/llvm-project/commit/51e5846b5645f4a7f6065df1cebaf2842222c180
DIFF: https://github.com/llvm/llvm-project/commit/51e5846b5645f4a7f6065df1cebaf2842222c180.diff
LOG: [RISCV][NFC] Renamed [Read/Write]VGather* -> [Read/Write]VRGatherV*
Differential Revision: https://reviews.llvm.org/D145402
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index d1d436bdd12f3..4d56482851a94 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -942,13 +942,13 @@ multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVGatherV_UpperBound, ReadVGatherV_UpperBound,
- ReadVGatherV_UpperBound, ReadVMask]>;
+ Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_UpperBound,
+ ReadVRGatherVV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVGatherX_UpperBound, ReadVGatherV_UpperBound,
- ReadVGatherX_UpperBound, ReadVMask]>;
+ Sched<[WriteVRGatherVX_UpperBound, ReadVRGatherVV_UpperBound,
+ ReadVRGatherVX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVGatherI_UpperBound, ReadVGatherV_UpperBound,
+ Sched<[WriteVRGatherVI_UpperBound, ReadVRGatherVV_UpperBound,
ReadVMask]>;
}
@@ -1662,8 +1662,8 @@ let Predicates = [HasVInstructions] in {
let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>;
def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
- Sched<[WriteVGatherV_UpperBound, ReadVGatherV_UpperBound,
- ReadVGatherV_UpperBound]>;
+ Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_UpperBound,
+ ReadVRGatherVV_UpperBound]>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
// Vector Compress Instruction
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 45ccbb7dd6ced..bdbb14c695cd2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1987,8 +1987,8 @@ multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVGatherV_MX = !cast<SchedWrite>("WriteVGatherV_" # mx);
- defvar ReadVGatherV_MX = !cast<SchedRead>("ReadVGatherV_" # mx);
+ defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
+ defvar ReadVRGatherVV_MX = !cast<SchedRead>("ReadVRGatherVV_" # mx);
foreach sew = EEWList in {
defvar octuple_lmul = m.octuple;
@@ -1998,7 +1998,8 @@ multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
defvar emulMX = octuple_to_str<octuple_emul>.ret;
defvar emul = !cast<LMULInfo>("V_" # emulMX);
defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint>,
- Sched<[WriteVGatherV_MX, ReadVGatherV_MX, ReadVGatherV_MX]>;
+ Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_MX,
+ ReadVRGatherVV_MX]>;
}
}
}
@@ -2394,18 +2395,20 @@ multiclass VPseudoBinaryM_VI<LMULInfo m> {
multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVGatherV_MX = !cast<SchedWrite>("WriteVGatherV_" # mx);
- defvar WriteVGatherX_MX = !cast<SchedWrite>("WriteVGatherX_" # mx);
- defvar WriteVGatherI_MX = !cast<SchedWrite>("WriteVGatherI_" # mx);
- defvar ReadVGatherV_MX = !cast<SchedRead>("ReadVGatherV_" # mx);
- defvar ReadVGatherX_MX = !cast<SchedRead>("ReadVGatherX_" # mx);
+ defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
+ defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
+ defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
+ defvar ReadVRGatherVV_MX = !cast<SchedRead>("ReadVRGatherVV_" # mx);
+ defvar ReadVRGatherVX_MX = !cast<SchedRead>("ReadVRGatherVX_" # mx);
defm "" : VPseudoBinaryV_VV<m, Constraint>,
- Sched<[WriteVGatherV_MX, ReadVGatherV_MX, ReadVGatherV_MX, ReadVMask]>;
+ Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_MX,
+ ReadVRGatherVV_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_VX<m, Constraint>,
- Sched<[WriteVGatherX_MX, ReadVGatherV_MX, ReadVGatherX_MX, ReadVMask]>;
+ Sched<[WriteVRGatherVX_MX, ReadVRGatherVV_MX,
+ ReadVRGatherVX_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
- Sched<[WriteVGatherI_MX, ReadVGatherV_MX, ReadVMask]>;
+ Sched<[WriteVRGatherVI_MX, ReadVRGatherVV_MX, ReadVMask]>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index faf690ae46fd5..78c608726a574 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -327,9 +327,9 @@ defm "" : LMULSchedWrites<"WriteVISlideI">;
defm "" : LMULSchedWrites<"WriteVISlide1X">;
defm "" : LMULSchedWrites<"WriteVFSlide1F">;
// 16.4. Vector Register Gather Instructions
-defm "" : LMULSchedWrites<"WriteVGatherV">;
-defm "" : LMULSchedWrites<"WriteVGatherX">;
-defm "" : LMULSchedWrites<"WriteVGatherI">;
+defm "" : LMULSchedWrites<"WriteVRGatherVV">;
+defm "" : LMULSchedWrites<"WriteVRGatherVX">;
+defm "" : LMULSchedWrites<"WriteVRGatherVI">;
// 16.5. Vector Compress Instruction
defm "" : LMULSchedWrites<"WriteVCompressV">;
// 16.6. Whole Vector Register Move
@@ -549,8 +549,8 @@ defm "" : LMULSchedReads<"ReadVISlideX">;
defm "" : LMULSchedReads<"ReadVFSlideV">;
defm "" : LMULSchedReads<"ReadVFSlideF">;
// 16.4. Vector Register Gather Instructions
-defm "" : LMULSchedReads<"ReadVGatherV">;
-defm "" : LMULSchedReads<"ReadVGatherX">;
+defm "" : LMULSchedReads<"ReadVRGatherVV">;
+defm "" : LMULSchedReads<"ReadVRGatherVX">;
// 16.5. Vector Compress Instruction
defm "" : LMULSchedReads<"ReadVCompressV">;
// 16.6. Whole Vector Register Move
@@ -741,9 +741,9 @@ defm "" : LMULWriteRes<"WriteVISlideX", []>;
defm "" : LMULWriteRes<"WriteVISlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
-defm "" : LMULWriteRes<"WriteVGatherV", []>;
-defm "" : LMULWriteRes<"WriteVGatherX", []>;
-defm "" : LMULWriteRes<"WriteVGatherI", []>;
+defm "" : LMULWriteRes<"WriteVRGatherVV", []>;
+defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
+defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
defm "" : LMULWriteRes<"WriteVCompressV", []>;
// These are already LMUL aware
def : WriteRes<WriteVMov1V, []>;
@@ -899,8 +899,8 @@ defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
-defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
-defm "" : LMULReadAdvance<"ReadVGatherX", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVV", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX", 0>;
defm "" : LMULReadAdvance<"ReadVCompressV", 0>;
// These are already LMUL aware
def : ReadAdvance<ReadVMov1V, 0>;
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