[PATCH] D146761: [AMDGPU] Make buffer intrinsics pointer-valued

Krzysztof Drewniak via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 24 12:06:53 PDT 2023 

krzysz00 updated this revision to Diff 508185.
krzysz00 added a comment.

Add tests for constructing buffer descriptors from integers


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146761/new/

https://reviews.llvm.org/D146761

Files:
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/test/Analysis/DivergenceAnalysis/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  llvm/test/Bitcode/upgrade-amdgpu-amdgcn-buffer-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
  llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
  llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
  llvm/test/CodeGen/AMDGPU/amdpal.ll
  llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
  llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
  llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
  llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
  llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
  llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
  llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
  llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
  llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
  llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
  llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
  llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
  llvm/test/CodeGen/AMDGPU/else.ll
  llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  llvm/test/CodeGen/AMDGPU/fail-select-buffer-atomic-fadd.ll
  llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
  llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
  llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
  llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
  llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
  llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
  llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
  llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
  llvm/test/CodeGen/AMDGPU/mubuf.ll
  llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
  llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
  llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
  llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
  llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
  llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
  llvm/test/CodeGen/AMDGPU/si-scheduler.ll
  llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
  llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/AMDGPU/split-smrd.ll
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
  llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
  llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
  llvm/test/CodeGen/AMDGPU/wait.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/AMDGPU/wqm.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
  llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
  llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll
  llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
  llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
  llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
  llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
  llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
  llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll
  llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll

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