[PATCH] D146711: [RISCV] Lower insert subvector shuffles as vslideups

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 24 11:37:09 PDT 2023

reames added a comment.

Looking at some code which benefits from this change, I noticed an opportunity for a follow up.

  vsetivli        zero, 4, e8, mf8, ta, ma
  vle8.v  v8, (a0)
  vle8.v  v10, (a4)
  vsetivli        zero, 8, e8, mf2, tu, ma
  vslideup.vi     v8, v10, 4

In the snippet above, the vslideup.vi does not need to be tail undisturbed.  All of the tail efforts are undef.

Not sure if this makes sense to handle during lowering, or as a general dag combine on vslide.vi when the destination has undef elements.  If we do it as a DAG combine, moving the suffix logic from this patch into the same place probably makes sense.

  rG LLVM Github Monorepo



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