[PATCH] D146711: [RISCV] Lower insert subvector shuffles as vslideups

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll:155
 ; ZVE32F-NEXT:    vslidedown.vi v9, v8, 2
-; ZVE32F-NEXT:    li a0, 2
-; ZVE32F-NEXT:    vmv.s.x v0, a0
-; ZVE32F-NEXT:    vrgather.vi v10, v8, 0
-; ZVE32F-NEXT:    vrgather.vi v10, v9, 0, v0.t
-; ZVE32F-NEXT:    vse32.v v10, (a1)
+; ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
+; ZVE32F-NEXT:    vslideup.vi v8, v9, 1
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So `rd=x0, rs1=x0` means to keep the existing VL. Could that mean these two vsetivli's could be merged into one `vsetivli zero, 2, e32, m1, tu, ma`, seeing as the second `tu` trumps the former `ta`?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D146711/new/

https://reviews.llvm.org/D146711