[llvm] 410a239 - [RISCV] Add test for shuffles that could be done as vmerges
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 24 02:15:09 PDT 2023
Author: Luke Lau
Date: 2023-03-24T09:15:03Z
New Revision: 410a239996725e68b431e7e3e43e270290be93d2
URL: https://github.com/llvm/llvm-project/commit/410a239996725e68b431e7e3e43e270290be93d2
DIFF: https://github.com/llvm/llvm-project/commit/410a239996725e68b431e7e3e43e270290be93d2.diff
LOG: [RISCV] Add test for shuffles that could be done as vmerges
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D146710
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
index 7b28ce7ad654c..9a1cfef9bbc83 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -644,3 +644,129 @@ entry:
%5 = shufflevector <4 x i16> %3, <4 x i16> %4, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
ret <4 x i16> %5
}
+
+define <8 x i8> @merge_start_into_end(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_start_into_end:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: li a0, 240
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vadd.vi v8, v11, -4
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+ ret <8 x i8> %res
+}
+
+define <8 x i8> @merge_start_into_end_non_contiguous(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_start_into_end_non_contiguous:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: li a0, 144
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vadd.vi v8, v11, -4
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 11>
+ ret <8 x i8> %res
+}
+
+define <8 x i8> @merge_end_into_end(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_end_into_end:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+ ret <8 x i8> %res
+}
+
+define <8 x i8> @merge_start_into_middle(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_start_into_middle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: li a0, 30
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vadd.vi v8, v11, -1
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7>
+ ret <8 x i8> %res
+}
+
+define <8 x i8> @merge_start_into_start(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_start_into_start:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 240
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i8> %res
+}
+
+define <8 x i8> @merge_slidedown(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_slidedown:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vadd.vi v12, v11, 1
+; CHECK-NEXT: li a0, 195
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 3, i32 4, i32 5, i32 6, i32 14, i32 15>
+ ret <8 x i8> %res
+}
+
+; This should slide %v down by 2 and %w up by 1 before merging them
+define <8 x i8> @merge_non_contiguous_slideup_slidedown(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: merge_non_contiguous_slideup_slidedown:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vadd.vi v12, v11, 2
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: li a0, 234
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vadd.vi v8, v11, -1
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 10, i32 6, i32 12, i32 13, i32 14>
+ ret <8 x i8> %res
+}
+
+; This shouldn't generate a vmerge because the elements of %w are not consecutive
+define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: unmergable:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vadd.vi v11, v10, 2
+; CHECK-NEXT: lui a0, %hi(.LCPI44_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI44_0)
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: li a0, 234
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: vrgather.vv v10, v9, v12, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 9, i32 4, i32 11, i32 6, i32 13, i32 8, i32 15>
+ ret <8 x i8> %res
+}
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