[PATCH] D92973: [RISCV] Add intrinsics for vsetvli instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D92973#4218408 <https://reviews.llvm.org/D92973#4218408>, @Origami404 wrote:

> In D92973#2447416 <https://reviews.llvm.org/D92973#2447416>, @evandro wrote:
>
>> The default should be `ta` and `mu`.  The compiler is usually agnostic about the tail of the vector, but usually assumes that masked elements are preserved.
>
> Hello! Sorry to bother everyone, but I want to know what should one use to set `ta/tu/ma/mu` if the intrinsic just make `ta` and `mu` as default?

ta ma is now the default.

The compiler will try to change it automatically based on the requirements of the intrinsics that use it.

In some regards the intrinsic shouldn’t be thought of as creating a vsetvli instruction directly. It’s an intrinsic to get the VL that a vsetvli would produce for the given AVL, SEW, and LMUL.


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  https://reviews.llvm.org/D92973/new/

https://reviews.llvm.org/D92973