[PATCH] D145299: [InstCombine] Generate better code for std::bit_ceil

[Kazu Hirata via Phabricator via llvm-commits]

kazu marked 2 inline comments as done.
kazu added inline comments.


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Comment at: llvm/test/Transforms/InstCombine/bit_ceil.ll:164
-; CHECK-NEXT:    [[UGT_INV:%.*]] = icmp ugt i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[UGT_INV]], i32 [[SHL]], i32 1
 ; CHECK-NEXT:    ret i32 [[SEL]]
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nikic wrote:
> The order gets canonicalized here. You can use something like `icmp slt %x, 0` to avoid.
I settled on `icmp eq %dec, 0`.  The order of the select operands seems to stick that way.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145299/new/

https://reviews.llvm.org/D145299