[llvm] 2cfd06b - [BoundsChecking] Don't crash on scalable vector sizes
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 23 08:53:53 PDT 2023
Author: Philip Reames
Date: 2023-03-23T08:53:41-07:00
New Revision: 2cfd06ba672f4e3097b6c2c576bdb876d37c71d1
URL: https://github.com/llvm/llvm-project/commit/2cfd06ba672f4e3097b6c2c576bdb876d37c71d1
DIFF: https://github.com/llvm/llvm-project/commit/2cfd06ba672f4e3097b6c2c576bdb876d37c71d1.diff
LOG: [BoundsChecking] Don't crash on scalable vector sizes
Added:
Modified:
llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
llvm/test/Instrumentation/BoundsChecking/simple.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp b/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
index 8b1d39ad412fa..04ffbf6636e1a 100644
--- a/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
+++ b/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
@@ -56,7 +56,7 @@ static Value *getBoundsCheckCond(Value *Ptr, Value *InstVal,
const DataLayout &DL, TargetLibraryInfo &TLI,
ObjectSizeOffsetEvaluator &ObjSizeEval,
BuilderTy &IRB, ScalarEvolution &SE) {
- uint64_t NeededSize = DL.getTypeStoreSize(InstVal->getType());
+ TypeSize NeededSize = DL.getTypeStoreSize(InstVal->getType());
LLVM_DEBUG(dbgs() << "Instrument " << *Ptr << " for " << Twine(NeededSize)
<< " bytes\n");
@@ -72,7 +72,7 @@ static Value *getBoundsCheckCond(Value *Ptr, Value *InstVal,
ConstantInt *SizeCI = dyn_cast<ConstantInt>(Size);
Type *IntTy = DL.getIntPtrType(Ptr->getType());
- Value *NeededSizeVal = ConstantInt::get(IntTy, NeededSize);
+ Value *NeededSizeVal = IRB.CreateTypeSize(IntTy, NeededSize);
auto SizeRange = SE.getUnsignedRange(SE.getSCEV(Size));
auto OffsetRange = SE.getUnsignedRange(SE.getSCEV(Offset));
diff --git a/llvm/test/Instrumentation/BoundsChecking/simple.ll b/llvm/test/Instrumentation/BoundsChecking/simple.ll
index 57858618d17b3..e329b90d0cde4 100644
--- a/llvm/test/Instrumentation/BoundsChecking/simple.ll
+++ b/llvm/test/Instrumentation/BoundsChecking/simple.ll
@@ -33,7 +33,7 @@ define void @f2() nounwind {
; CHECK-NEXT: store i32 3, ptr [[IDX]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5:[0-9]+]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6:[0-9]+]]
; CHECK-NEXT: unreachable
;
%1 = tail call ptr @malloc(i64 32)
@@ -57,7 +57,7 @@ define void @f3(i64 %x) nounwind {
; CHECK-NEXT: store i32 3, ptr [[IDX]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = tail call ptr @calloc(i64 4, i64 %x)
@@ -93,7 +93,7 @@ define void @f4(i64 %x) nounwind {
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[IDX]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = tail call ptr @realloc(ptr null, i64 %x) nounwind
@@ -115,7 +115,7 @@ define void @f5(i64 %x) nounwind {
; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[IDX]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%idx = getelementptr inbounds [8 x i8], ptr @.str, i64 0, i64 %x
@@ -137,7 +137,7 @@ define void @f5_as1(i64 %x) nounwind {
; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr addrspace(1) [[IDX]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%idx = getelementptr inbounds [8 x i8], ptr addrspace(1) @.str_as1, i64 0, i64 %x
@@ -169,7 +169,7 @@ define void @f7(i64 %x) nounwind {
; CHECK-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = alloca i128, i64 %x
@@ -222,7 +222,7 @@ define void @f10(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: [[TMP12:%.*]] = load i128, ptr [[TMP6]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = alloca i128, i64 %x
@@ -240,7 +240,7 @@ define void @f11(ptr byval(i128) %x) nounwind {
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP1]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = getelementptr inbounds i8, ptr %x, i64 16
@@ -256,7 +256,7 @@ define void @f11_as1(ptr addrspace(1) byval(i128) %x) nounwind {
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr addrspace(1) [[TMP1]], align 4
; CHECK-NEXT: ret void
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = getelementptr inbounds i8, ptr addrspace(1) %x, i16 16
@@ -282,7 +282,7 @@ define i64 @f12(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP4]], align 8
; CHECK-NEXT: ret i64 [[TMP12]]
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
%1 = tail call ptr @calloc(i64 1, i64 %x)
@@ -354,7 +354,7 @@ define i8 @f14(i1 %i) {
; CHECK-NEXT: [[RET:%.*]] = load i8, ptr [[P]], align 1
; CHECK-NEXT: ret i8 [[RET]]
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
entry:
@@ -396,7 +396,7 @@ define i8 @f15(i1 %i) {
; CHECK-NEXT: [[RET:%.*]] = load i8, ptr [[ALLOC]], align 1
; CHECK-NEXT: ret i8 [[RET]]
; CHECK: trap:
-; CHECK-NEXT: call void @llvm.trap() #[[ATTR5]]
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
; CHECK-NEXT: unreachable
;
entry:
@@ -414,3 +414,53 @@ bb2:
%ret = load i8, ptr %alloc
ret i8 %ret
}
+
+define <4 x i32> @load_vector(i64 %y) nounwind {
+; CHECK-LABEL: @load_vector(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call ptr @calloc(i64 1, i64 256)
+; CHECK-NEXT: [[DOTIDX:%.*]] = mul i64 [[Y:%.*]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[DOTIDX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 [[Y]]
+; CHECK-NEXT: [[TMP4:%.*]] = sub i64 256, [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i64 256, [[TMP2]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i64 [[TMP4]], 16
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[TRAP:%.*]], label [[TMP8:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr [[TMP3]], align 8
+; CHECK-NEXT: ret <4 x i32> [[TMP9]]
+; CHECK: trap:
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
+; CHECK-NEXT: unreachable
+;
+ %1 = tail call ptr @calloc(i64 1, i64 256)
+ %2 = getelementptr inbounds i64, ptr %1, i64 %y
+ %3 = load <4 x i32>, ptr %2, align 8
+ ret <4 x i32> %3
+}
+
+define <vscale x 1 x i32> @load_scalable_vector(i64 %y) nounwind {
+; CHECK-LABEL: @load_scalable_vector(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call ptr @calloc(i64 1, i64 256)
+; CHECK-NEXT: [[DOTIDX:%.*]] = mul i64 [[Y:%.*]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[DOTIDX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 [[Y]]
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4
+; CHECK-NEXT: [[TMP6:%.*]] = sub i64 256, [[TMP2]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 256, [[TMP2]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TRAP:%.*]], label [[TMP10:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = load <vscale x 1 x i32>, ptr [[TMP3]], align 8
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP11]]
+; CHECK: trap:
+; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
+; CHECK-NEXT: unreachable
+;
+ %1 = tail call ptr @calloc(i64 1, i64 256)
+ %2 = getelementptr inbounds i64, ptr %1, i64 %y
+ %3 = load <vscale x 1 x i32>, ptr %2, align 8
+ ret <vscale x 1 x i32> %3
+}
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