[PATCH] D145299: [InstCombine] Generate better code for std::bit_ceil

[Nikita Popov via Phabricator via llvm-commits]

nikic accepted this revision.
nikic added a comment.

LG



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Comment at: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp:3193-3227
+  // Match the operation that's used to compute CtlzOp from CommonAncestor.  If
+  // a match is found, execute the operation on CR, update CR, and return true.
+  // Otherwise, return false.
+  auto MatchForward = [&](Value *CommonAncestor) {
+    const APInt *C = nullptr;
+    if (match(CtlzOp, m_Add(m_Specific(CommonAncestor), m_APInt(C)))) {
+      CR = CR.add(*C);
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To clarify, this is what I meant.


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Comment at: llvm/test/Transforms/InstCombine/bit_ceil.ll:164
-; CHECK-NEXT:    [[UGT_INV:%.*]] = icmp ugt i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[UGT_INV]], i32 [[SHL]], i32 1
 ; CHECK-NEXT:    ret i32 [[SEL]]
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The order gets canonicalized here. You can use something like `icmp slt %x, 0` to avoid.


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https://reviews.llvm.org/D145299