[PATCH] D146636: Precommit tests for #60690

[Jun Zhang via Phabricator via llvm-commits]

junaire updated this revision to Diff 507605.
junaire added a comment.

1. Use more meaningful name for the tests
2. Add fshr case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146636/new/

https://reviews.llvm.org/D146636

Files:
  llvm/test/Transforms/InstCombine/bswap.ll


Index: llvm/test/Transforms/InstCombine/bswap.ll
===================================================================
--- llvm/test/Transforms/InstCombine/bswap.ll
+++ llvm/test/Transforms/InstCombine/bswap.ll
@@ -929,3 +929,63 @@
   %t6 = trunc i64 %t5 to i32
   ret i32 %t6
 }
+
+define i64 @PR60690_call_fshl(i64 %result) {
+; CHECK-LABEL: @PR60690_call_fshl(
+; CHECK-NEXT:    [[AND_I:%.*]] = lshr i64 [[RESULT:%.*]], 8
+; CHECK-NEXT:    [[SHR_I:%.*]] = and i64 [[AND_I]], 71777214294589695
+; CHECK-NEXT:    [[AND1_I:%.*]] = shl i64 [[RESULT]], 8
+; CHECK-NEXT:    [[SHL_I:%.*]] = and i64 [[AND1_I]], -71777214294589696
+; CHECK-NEXT:    [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]
+; CHECK-NEXT:    [[AND_I7:%.*]] = shl i64 [[OR_I]], 16
+; CHECK-NEXT:    [[SHL_I8:%.*]] = and i64 [[AND_I7]], -281470681808896
+; CHECK-NEXT:    [[AND1_I9:%.*]] = lshr i64 [[OR_I]], 16
+; CHECK-NEXT:    [[SHR_I10:%.*]] = and i64 [[AND1_I9]], 281470681808895
+; CHECK-NEXT:    [[OR_I11:%.*]] = or i64 [[SHL_I8]], [[SHR_I10]]
+; CHECK-NEXT:    [[OR_I12:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[OR_I11]], i64 [[OR_I11]], i64 32)
+; CHECK-NEXT:    ret i64 [[OR_I12]]
+;
+  %and.i = lshr i64 %result, 8
+  %shr.i = and i64 %and.i, 71777214294589695
+  %and1.i = shl i64 %result, 8
+  %shl.i = and i64 %and1.i, -71777214294589696
+  %or.i = or i64 %shr.i, %shl.i
+  %and.i7 = shl i64 %or.i, 16
+  %shl.i8 = and i64 %and.i7, -281470681808896
+  %and1.i9 = lshr i64 %or.i, 16
+  %shr.i10 = and i64 %and1.i9, 281470681808895
+  %or.i11 = or i64 %shl.i8, %shr.i10
+  %or.i12 = tail call i64 @llvm.fshl.i64(i64 %or.i11, i64 %or.i11, i64 32)
+  ret i64 %or.i12
+}
+declare i64 @llvm.fshl.i64(i64, i64, i64)
+
+define i64 @PR60690_call_fshr(i64 %result) {
+; CHECK-LABEL: @PR60690_call_fshr(
+; CHECK-NEXT:    [[AND_I:%.*]] = lshr i64 [[RESULT:%.*]], 8
+; CHECK-NEXT:    [[SHR_I:%.*]] = and i64 [[AND_I]], 71777214294589695
+; CHECK-NEXT:    [[AND1_I:%.*]] = shl i64 [[RESULT]], 8
+; CHECK-NEXT:    [[SHL_I:%.*]] = and i64 [[AND1_I]], -71777214294589696
+; CHECK-NEXT:    [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]
+; CHECK-NEXT:    [[AND_I7:%.*]] = shl i64 [[OR_I]], 16
+; CHECK-NEXT:    [[SHL_I8:%.*]] = and i64 [[AND_I7]], -281470681808896
+; CHECK-NEXT:    [[AND1_I9:%.*]] = lshr i64 [[OR_I]], 16
+; CHECK-NEXT:    [[SHR_I10:%.*]] = and i64 [[AND1_I9]], 281470681808895
+; CHECK-NEXT:    [[OR_I11:%.*]] = or i64 [[SHL_I8]], [[SHR_I10]]
+; CHECK-NEXT:    [[OR_I12:%.*]] = call i64 @llvm.fshl.i64(i64 [[OR_I11]], i64 [[OR_I11]], i64 32)
+; CHECK-NEXT:    ret i64 [[OR_I12]]
+;
+  %and.i = lshr i64 %result, 8
+  %shr.i = and i64 %and.i, 71777214294589695
+  %and1.i = shl i64 %result, 8
+  %shl.i = and i64 %and1.i, -71777214294589696
+  %or.i = or i64 %shr.i, %shl.i
+  %and.i7 = shl i64 %or.i, 16
+  %shl.i8 = and i64 %and.i7, -281470681808896
+  %and1.i9 = lshr i64 %or.i, 16
+  %shr.i10 = and i64 %and1.i9, 281470681808895
+  %or.i11 = or i64 %shl.i8, %shr.i10
+  %or.i12 = tail call i64 @llvm.fshr.i64(i64 %or.i11, i64 %or.i11, i64 32)
+  ret i64 %or.i12
+}
+declare i64 @llvm.fshr.i64(i64, i64, i64)


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