[PATCH] D146627: [RISCV] Combine (vrgather src, vid) -> vmerge
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 22 20:30:20 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11055
+ break;
+ return DAG.getNode(RISCVISD::VP_MERGE_VL, SDLoc(N), N->getValueType(0),
+ Mask, N->getOperand(0), N->getOperand(2), VL);
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I'm not sure you want VP_MERGE_VL here. VP_MERGE_VL is supposed to be tail undisturbed. I think you want RISCVISD::VSELECT_VL.
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Comment at: llvm/test/CodeGen/RISCV/rvv/combine-gather.ll:18
; CHECK-NEXT: ret
%res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
ret <8 x i8> %res
----------------
Shouldn't we be able to implement this shuffle with vslideup/down?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D146627/new/
https://reviews.llvm.org/D146627
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