[llvm] 164b046 - [RISCV] Convert segment registers to VR registers in RISCVMCInstLower.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-22T10:08:03-07:00
New Revision: 164b046ebfa8d7ad36ce567e2214c97e4e7b1657

URL: https://github.com/llvm/llvm-project/commit/164b046ebfa8d7ad36ce567e2214c97e4e7b1657
DIFF: https://github.com/llvm/llvm-project/commit/164b046ebfa8d7ad36ce567e2214c97e4e7b1657.diff

LOG: [RISCV] Convert segment registers to VR registers in RISCVMCInstLower.

Similar to what we do for the LMUL>1 register classes. The printing
is only working today because the segment registers have "ABI" names
set to their base register name.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
index 281918259cdb3..6b658539a319b 100644
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -193,6 +193,19 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
       } else if (RISCV::FPR64RegClass.contains(Reg)) {
         Reg = TRI->getSubReg(Reg, RISCV::sub_32);
         assert(Reg && "Superregister does not exist");
+      } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
+                 RISCV::VRN2M2RegClass.contains(Reg) ||
+                 RISCV::VRN2M4RegClass.contains(Reg) ||
+                 RISCV::VRN3M1RegClass.contains(Reg) ||
+                 RISCV::VRN3M2RegClass.contains(Reg) ||
+                 RISCV::VRN4M1RegClass.contains(Reg) ||
+                 RISCV::VRN4M2RegClass.contains(Reg) ||
+                 RISCV::VRN5M1RegClass.contains(Reg) ||
+                 RISCV::VRN6M1RegClass.contains(Reg) ||
+                 RISCV::VRN7M1RegClass.contains(Reg) ||
+                 RISCV::VRN8M1RegClass.contains(Reg)) {
+        Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
+        assert(Reg && "Subregister does not exist");
       }
 
       MCOp = MCOperand::createReg(Reg);