[llvm] 2023cc2 - [RISCV] Clear mayRaiseFPException for Zfa fmvh.x.d and fmvp.d.x instructions.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-21T19:42:27-07:00
New Revision: 2023cc2b1b3ce2223091024f1687704948c4145f

URL: https://github.com/llvm/llvm-project/commit/2023cc2b1b3ce2223091024f1687704948c4145f
DIFF: https://github.com/llvm/llvm-project/commit/2023cc2b1b3ce2223091024f1687704948c4145f.diff

LOG: [RISCV] Clear mayRaiseFPException for Zfa fmvh.x.d and fmvp.d.x instructions.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 751a0eabbd39..ae38fd5c5dc2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -127,10 +127,13 @@ def FLEQ_D : FPCmp_rr<0b1010001, 0b100, "fleq.d", FPR64>;
 } // Predicates = [HasStdExtZfa, HasStdExtD]
 
 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
+let mayRaiseFPException = 0 in {
 def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
                Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
                Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
+}
+
 let isCodeGenOnly = 1, mayRaiseFPException = 0 in
 def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64,
                                 "fmv.x.w">,