[PATCH] D146523: [AMDGPU]: Add new intrinsic llvm.amdgcn.convergent.copy

[Jay Foad via Phabricator via llvm-commits]

foad added subscribers: cdevadas, ruiling.
foad added a comment.

In D146523#4210124 <https://reviews.llvm.org/D146523#4210124>, @pravinjagtap wrote:

> In D146523#4209889 <https://reviews.llvm.org/D146523#4209889>, @foad wrote:
>
>> In D146523#4209735 <https://reviews.llvm.org/D146523#4209735>, @pravinjagtap wrote:
>>
>>> In D146523#4209684 <https://reviews.llvm.org/D146523#4209684>, @foad wrote:
>>>
>>>> What does this do and what is it for?
>>>
>>> This convergent copy intrinsic will acts here as a form of barrier which makes sure that all the active lanes  of VGPR (i.e. result of intrinsic) is computed before its use.
>>
>> Can you give an example?
>
> Consider following input llvm IR:
>
>   %sub.i = sub nsw i32 0, %11
>   %12 = atomicrmw add ptr addrspace(1) %1, i32 %sub.i syncscope("agent-one-as") monotonic, align 4
>
> Here, I am transforming computation of  `%12` into a `for` loop which will executed by only a first active lane. One of the Basic Blocks associated with this for loop needs to read values from a VGPR (use) corresponding to `%sub.i`.
>
> So with the convergent copy I want to make sure that:
>
> 1. All lanes of a VGPR associated with `%sub.i`  are computed before starting the loop.
> 2. It will also stop sinking the computation of `%sub.i`  into basic blocks associated with that for loop.

And you want to use @llvm.amdgcn.readlane inside the loop to read arbitrary (probably inactive) lanes from %sub.i ?

I'm not sure that this is a robust solution. What about an example like this:

  %sub.i = sub nsw i32 0, %11
  %cc = call @llvm.amdgcn.convergent.copy(%sub.i)
  if (divergent condition) {
    some code here
  } else {
    ... = call @llvm.amdgcn.readlane(%cc, %n)
  }

What's to stop "some code here" from clobbering some lanes of the vgpr that was holding %cc?

Adding @ruiling @cdevadas


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