[PATCH] D146529: [RISCV][NFC] Add test case for SLP reduction vectorization failure

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll:846
+;   %3 = shufflevector <2 x i32> %1, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+;   %4 = insertelement <4 x i32> %3, i32 %x.2, i32 2
+;   %5 = insertelement <4 x i32> %4, i32 %x.3, i32 3
----------------
I just want to point out that this is a very weird bit of code.  We generate one pair of vector loads, but we could have generated the four scalar loads as a two vector loads as well.  What we model as a vector load + two inserts of scalars could easily be two vector loads and a concat of two vectors.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146529/new/

https://reviews.llvm.org/D146529