[PATCH] D146531: [AArch64][GlobalISel] Add support for some across-vector NEON intrinsics

[Vladislav Dzhidzhoev via Phabricator via llvm-commits]

dzhidzhoev created this revision.
dzhidzhoev added reviewers: paquette, aemerson, t.p.northover, arsenm, kazu, sunfish, ab, sdesmalen.
Herald added subscribers: hiraditya, kristof.beyls, dschuff.
Herald added a project: All.
dzhidzhoev requested review of this revision.
Herald added subscribers: llvm-commits, aheejin, wdng.
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Support uaddv, saddv, umaxv, smaxv, uminv, sminv, fmaxv, fminv,
fmaxnmv, fminnmv intrinsics in GlobalISel.

GlobalISelEmitter couldn't import SelectionDAG patterns containing nodes
with 8-bit result type, since they had untyped values. Therefore, MVT
for the f8 type has been added to eliminate untyped nodes in these
patterns.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146531

Files:
  llvm/include/llvm/CodeGen/ValueTypes.td
  llvm/include/llvm/Support/MachineValueType.h
  llvm/lib/Target/AArch64/AArch64InstrGISel.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/arm64-fminv.ll
  llvm/test/CodeGen/AArch64/arm64-neon-across.ll
  llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
  llvm/utils/TableGen/CodeGenTarget.cpp

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