[PATCH] D143723: [RISCV] Increase default vectorizer LMUL to 2

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 506921.
luke added a comment.

Update SLP test case

SLP calls this hook too to work out the max vec reg size.
With LMUL=2, the test case now has 128*2 = 256 bits to work with per "register", so it can now vectorize those 4 i64 stores.
Note that this doesn't actually change the generated code, both -riscv-v-register-bit-width-lmul=1 and -riscv-v-register-bit-width-lmul=2 produce the following:

foo:

  vsetivli        zero, 4, e64, m2, ta, ma
  vmv.v.i v8, 0
  vse64.v v8, (a0)
  ret


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143723/new/

https://reviews.llvm.org/D143723

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
  llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
  llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
  llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
  llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
  llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
  llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll
  llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
  llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
  llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
  llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
  llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
  llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
  llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll
  llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll

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