[llvm] 9c93e72 - llvm-tblgen: Rewrite emitters to use `TableGen::Emitter`
NAKAMURA Takumi via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 21 00:22:28 PDT 2023
Author: NAKAMURA Takumi
Date: 2023-03-21T16:21:27+09:00
New Revision: 9c93e728bfb8079c1de51e5481168c4083038c2a
URL: https://github.com/llvm/llvm-project/commit/9c93e728bfb8079c1de51e5481168c4083038c2a
DIFF: https://github.com/llvm/llvm-project/commit/9c93e728bfb8079c1de51e5481168c4083038c2a.diff
LOG: llvm-tblgen: Rewrite emitters to use `TableGen::Emitter`
Each emitter became self-contained since it has the registration of option.
Differential Revision: https://reviews.llvm.org/D144351
Added:
Modified:
llvm/utils/TableGen/AsmMatcherEmitter.cpp
llvm/utils/TableGen/AsmWriterEmitter.cpp
llvm/utils/TableGen/Attributes.cpp
llvm/utils/TableGen/CTagsEmitter.cpp
llvm/utils/TableGen/CallingConvEmitter.cpp
llvm/utils/TableGen/CodeEmitterGen.cpp
llvm/utils/TableGen/CompressInstEmitter.cpp
llvm/utils/TableGen/DAGISelEmitter.cpp
llvm/utils/TableGen/DFAEmitter.cpp
llvm/utils/TableGen/DFAPacketizerEmitter.cpp
llvm/utils/TableGen/DXILEmitter.cpp
llvm/utils/TableGen/DirectiveEmitter.cpp
llvm/utils/TableGen/DisassemblerEmitter.cpp
llvm/utils/TableGen/ExegesisEmitter.cpp
llvm/utils/TableGen/FastISelEmitter.cpp
llvm/utils/TableGen/GICombinerEmitter.cpp
llvm/utils/TableGen/GlobalISelEmitter.cpp
llvm/utils/TableGen/InstrDocsEmitter.cpp
llvm/utils/TableGen/InstrInfoEmitter.cpp
llvm/utils/TableGen/IntrinsicEmitter.cpp
llvm/utils/TableGen/OptParserEmitter.cpp
llvm/utils/TableGen/OptRSTEmitter.cpp
llvm/utils/TableGen/PseudoLoweringEmitter.cpp
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
llvm/utils/TableGen/RegisterBankEmitter.cpp
llvm/utils/TableGen/RegisterInfoEmitter.cpp
llvm/utils/TableGen/SearchableTableEmitter.cpp
llvm/utils/TableGen/SubtargetEmitter.cpp
llvm/utils/TableGen/TableGen.cpp
llvm/utils/TableGen/TableGenBackends.h
llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
llvm/utils/TableGen/X86MnemonicTables.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 6bffd545f3c4..a1082674ddf1 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -100,7 +100,6 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "SubtargetFeatureInfo.h"
-#include "TableGenBackends.h"
#include "Types.h"
#include "llvm/ADT/CachedHashString.h"
#include "llvm/ADT/PointerUnion.h"
@@ -108,7 +107,6 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
-#include "llvm/Config/llvm-config.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
@@ -4004,10 +4002,5 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
}
-namespace llvm {
-
-void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
- AsmMatcherEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<AsmMatcherEmitter>
+ X("gen-asm-matcher", "Generate assembly instruction matcher");
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 0d5109f9b3c9..505fdd8c25fb 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -17,7 +17,6 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "SequenceToOffsetTable.h"
-#include "TableGenBackends.h"
#include "Types.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
@@ -1310,10 +1309,5 @@ void AsmWriterEmitter::run(raw_ostream &O) {
EmitPrintAliasInstruction(O);
}
-namespace llvm {
-
-void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
- AsmWriterEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<AsmWriterEmitter>
+ X("gen-asm-writer", "Generate assembly writer");
diff --git a/llvm/utils/TableGen/Attributes.cpp b/llvm/utils/TableGen/Attributes.cpp
index 705fb0041585..5f8dd1594a1f 100644
--- a/llvm/utils/TableGen/Attributes.cpp
+++ b/llvm/utils/TableGen/Attributes.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "TableGenBackends.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <vector>
using namespace llvm;
@@ -130,10 +130,5 @@ void Attributes::run(raw_ostream &OS) {
emitAttributeProperties(OS);
}
-namespace llvm {
-
-void EmitAttributes(RecordKeeper &RK, raw_ostream &OS) {
- Attributes(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<Attributes> X("gen-attrs",
+ "Generate attributes");
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index 11ec81790877..b8e27d057d95 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -12,11 +12,11 @@
//
//===----------------------------------------------------------------------===//
-#include "TableGenBackends.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
#include <vector>
using namespace llvm;
@@ -86,8 +86,5 @@ void CTagsEmitter::run(raw_ostream &OS) {
T.emit(OS);
}
-namespace llvm {
-
-void EmitCTags(RecordKeeper &RK, raw_ostream &OS) { CTagsEmitter(RK).run(OS); }
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<CTagsEmitter>
+ X("gen-ctags", "Generate ctags-compatible index");
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index 048cccc07c70..49d4f3196e66 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -429,10 +428,5 @@ void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
}
}
-namespace llvm {
-
-void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS) {
- CallingConvEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<CallingConvEmitter>
+ X("gen-callingconv", "Generate calling convention descriptions");
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 4bbc26018617..66ef71a90a93 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -16,7 +16,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
-#include "TableGenBackends.h"
#include "VarLenCodeEmitterGen.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
@@ -504,10 +503,5 @@ void CodeEmitterGen::run(raw_ostream &o) {
} // end anonymous namespace
-namespace llvm {
-
-void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
- CodeEmitterGen(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<CodeEmitterGen>
+ X("gen-emitter", "Generate machine code emitter");
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 89e50ea29cb1..a7816c24f871 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -67,7 +67,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
@@ -904,10 +903,5 @@ void CompressInstEmitter::run(raw_ostream &o) {
emitCompressInstEmitter(o, EmitterType::CheckCompress);
}
-namespace llvm {
-
-void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS) {
- CompressInstEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<CompressInstEmitter>
+ X("gen-compress-inst-emitter", "Generate RISCV compressed instructions.");
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 9ed9f5e88cea..cf8e3f267571 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -14,7 +14,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "DAGISelMatcher.h"
-#include "TableGenBackends.h"
#include "llvm/Support/Debug.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -188,10 +187,5 @@ void DAGISelEmitter::run(raw_ostream &OS) {
EmitMatcherTable(TheMatcher.get(), CGP, OS);
}
-namespace llvm {
-
-void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS) {
- DAGISelEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<DAGISelEmitter>
+ X("gen-dag-isel", "Generate a DAG instruction selector");
diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp
index 705908226fa1..54ad81cbebe8 100644
--- a/llvm/utils/TableGen/DFAEmitter.cpp
+++ b/llvm/utils/TableGen/DFAEmitter.cpp
@@ -22,13 +22,13 @@
#include "DFAEmitter.h"
#include "SequenceToOffsetTable.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/UniqueVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <cassert>
#include <cstdint>
#include <deque>
@@ -370,10 +370,5 @@ void CustomDfaEmitter::printActionValue(action_type A, raw_ostream &OS) {
OS << ")";
}
-namespace llvm {
-
-void EmitAutomata(RecordKeeper &RK, raw_ostream &OS) {
- AutomatonEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<AutomatonEmitter>
+ X("gen-automata", "Generate generic automata");
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 941846eca0fa..da8538fc801a 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -17,7 +17,6 @@
#include "CodeGenSchedule.h"
#include "CodeGenTarget.h"
#include "DFAEmitter.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -354,10 +353,5 @@ void DFAPacketizerEmitter::emitForItineraries(
<< "\n}\n\n";
}
-namespace llvm {
-
-void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
- DFAPacketizerEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<DFAPacketizerEmitter>
+ X("gen-dfa-packetizer", "Generate DFA Packetizer for VLIW targets");
diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp
index 5239cb74d2aa..51924ff76524 100644
--- a/llvm/utils/TableGen/DXILEmitter.cpp
+++ b/llvm/utils/TableGen/DXILEmitter.cpp
@@ -12,13 +12,13 @@
//===----------------------------------------------------------------------===//
#include "SequenceToOffsetTable.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/DXILOperationCommon.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
using namespace llvm::dxil;
@@ -411,9 +411,7 @@ static void emitDXILOperationTable(std::vector<DXILOperationData> &DXILOps,
OS << "}\n ";
}
-namespace llvm {
-
-void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
std::vector<Record *> Ops = Records.getAllDerivedDefinitions("dxil_op");
OS << "// Generated code, do not edit.\n";
OS << "\n";
@@ -439,4 +437,5 @@ void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
OS << "\n";
}
-} // namespace llvm
+static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation,
+ "Generate DXIL operation information");
diff --git a/llvm/utils/TableGen/DirectiveEmitter.cpp b/llvm/utils/TableGen/DirectiveEmitter.cpp
index a65c71690b09..9d2860743308 100644
--- a/llvm/utils/TableGen/DirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/DirectiveEmitter.cpp
@@ -12,13 +12,13 @@
//===----------------------------------------------------------------------===//
#include "llvm/TableGen/DirectiveEmitter.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
@@ -174,11 +174,9 @@ bool DirectiveLanguage::HasValidityErrors() const {
return HasDuplicateClausesInDirectives(getDirectives());
}
-namespace llvm {
-
// Generate the declaration section for the enumeration in the directive
// language
-void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
const auto DirLang = DirectiveLanguage{Records};
if (DirLang.HasValidityErrors())
return;
@@ -247,8 +245,6 @@ void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
OS << "#endif // LLVM_" << DirLang.getName() << "_INC\n";
}
-} // namespace llvm
-
// Generate function implementation for get<Enum>Name(StringRef Str)
static void GenerateGetName(const std::vector<Record *> &Records,
raw_ostream &OS, StringRef Enum,
@@ -877,11 +873,9 @@ void EmitDirectivesBasicImpl(const DirectiveLanguage &DirLang,
GenerateIsAllowedClause(DirLang, OS);
}
-namespace llvm {
-
// Generate the implemenation section for the enumeration in the directive
// language.
-void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
const auto DirLang = DirectiveLanguage{Records};
if (DirLang.HasValidityErrors())
return;
@@ -893,4 +887,10 @@ void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
EmitDirectivesBasicImpl(DirLang, OS);
}
-} // namespace llvm
+static TableGen::Emitter::Opt
+ X("gen-directive-decl", EmitDirectivesDecl,
+ "Generate directive related declaration code (header file)");
+
+static TableGen::Emitter::Opt
+ Y("gen-directive-impl", EmitDirectivesImpl,
+ "Generate directive related implementation code");
diff --git a/llvm/utils/TableGen/DisassemblerEmitter.cpp b/llvm/utils/TableGen/DisassemblerEmitter.cpp
index eba6c54bd385..92f3721507e5 100644
--- a/llvm/utils/TableGen/DisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/DisassemblerEmitter.cpp
@@ -94,9 +94,7 @@ using namespace llvm::X86Disassembler;
/// X86RecognizableInstr.cpp contains the implementation for a single
/// instruction.
-namespace llvm {
-
-void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
CodeGenTarget Target(Records);
emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS);
@@ -133,4 +131,5 @@ void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
EmitDecoder(Records, OS, PredicateNamespace);
}
-} // end namespace llvm
+static TableGen::Emitter::Opt X("gen-disassembler", EmitDisassembler,
+ "Generate disassembler");
diff --git a/llvm/utils/TableGen/ExegesisEmitter.cpp b/llvm/utils/TableGen/ExegesisEmitter.cpp
index 751000f726f2..736f1220be14 100644
--- a/llvm/utils/TableGen/ExegesisEmitter.cpp
+++ b/llvm/utils/TableGen/ExegesisEmitter.cpp
@@ -10,7 +10,6 @@
//
//===----------------------------------------------------------------------===//
-#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringRef.h"
@@ -203,10 +202,5 @@ void ExegesisEmitter::run(raw_ostream &OS) const {
} // end anonymous namespace
-namespace llvm {
-
-void EmitExegesis(RecordKeeper &RK, raw_ostream &OS) {
- ExegesisEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<ExegesisEmitter>
+ X("gen-exegesis", "Generate llvm-exegesis tables");
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index a1e45be609cd..3f3a63de0c0c 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -21,7 +21,6 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Error.h"
@@ -858,9 +857,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
// TODO: SignaturesWithConstantForms should be empty here.
}
-namespace llvm {
-
-void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
CodeGenDAGPatterns CGP(RK);
const CodeGenTarget &Target = CGP.getTargetInfo();
emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
@@ -876,4 +873,5 @@ void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
F.printFunctionDefinitions(OS);
}
-} // namespace llvm
+static TableGen::Emitter::Opt X("gen-fast-isel", EmitFastISel,
+ "Generate a \"fast\" instruction selector");
diff --git a/llvm/utils/TableGen/GICombinerEmitter.cpp b/llvm/utils/TableGen/GICombinerEmitter.cpp
index 68a7296de13a..be8425e304e6 100644
--- a/llvm/utils/TableGen/GICombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GICombinerEmitter.cpp
@@ -20,7 +20,6 @@
#include "GlobalISel/GIMatchDagOperands.h"
#include "GlobalISel/GIMatchDagPredicate.h"
#include "GlobalISel/GIMatchTree.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSet.h"
@@ -1067,8 +1066,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
//===----------------------------------------------------------------------===//
-namespace llvm {
-void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS) {
CodeGenTarget Target(RK);
emitSourceFileHeader("Global Combiner", OS);
@@ -1083,4 +1081,5 @@ void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS) {
NumPatternTotalStatistic = NumPatternTotal;
}
-} // namespace llvm
+static TableGen::Emitter::Opt X("gen-global-isel-combiner", EmitGICombiner,
+ "Generate GlobalISel combiner");
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index dfeb7aaeeda9..666253ac43b3 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -36,7 +36,6 @@
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
#include "SubtargetFeatureInfo.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/CodeGenCoverage.h"
#include "llvm/Support/CommandLine.h"
@@ -6363,8 +6362,5 @@ unsigned OperandMatcher::getInsnVarID() const { return Insn.getInsnVarID(); }
//===----------------------------------------------------------------------===//
-namespace llvm {
-void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS) {
- GlobalISelEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<GlobalISelEmitter>
+ X("gen-global-isel", "Generate GlobalISel selector");
diff --git a/llvm/utils/TableGen/InstrDocsEmitter.cpp b/llvm/utils/TableGen/InstrDocsEmitter.cpp
index 7476422025fd..616e7b589288 100644
--- a/llvm/utils/TableGen/InstrDocsEmitter.cpp
+++ b/llvm/utils/TableGen/InstrDocsEmitter.cpp
@@ -21,8 +21,8 @@
#include "CodeGenDAGPatterns.h"
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <string>
#include <vector>
@@ -54,9 +54,7 @@ static std::string escapeForRST(StringRef Str) {
return Result;
}
-namespace llvm {
-
-void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
CodeGenDAGPatterns CDP(RK);
CodeGenTarget &Target = CDP.getTargetInfo();
unsigned VariantCount = Target.getAsmParserVariantCount();
@@ -217,4 +215,5 @@ void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
}
}
-} // end namespace llvm
+static TableGen::Emitter::Opt X("gen-instr-docs", EmitInstrDocs,
+ "Generate instruction documentation");
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 4eef1fef2a91..c05177589024 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -1245,13 +1245,12 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
}
-namespace llvm {
-
-void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
RK.startTimer("Analyze DAG patterns");
InstrInfoEmitter(RK).run(OS);
RK.startTimer("Emit map table");
EmitMapTable(RK, OS);
}
-} // end namespace llvm
+static TableGen::Emitter::Opt X("gen-instr-info", EmitInstrInfo,
+ "Generate instruction descriptions");
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
index b759c7181112..704c12611fde 100644
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -12,7 +12,6 @@
#include "CodeGenIntrinsics.h"
#include "SequenceToOffsetTable.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
@@ -967,10 +966,16 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
OS << "#endif\n\n";
}
-void llvm::EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS) {
IntrinsicEmitter(RK).run(OS, /*Enums=*/true);
}
-void llvm::EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS) {
+static TableGen::Emitter::Opt X("gen-intrinsic-enums", EmitIntrinsicEnums,
+ "Generate intrinsic enums");
+
+static void EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS) {
IntrinsicEmitter(RK).run(OS, /*Enums=*/false);
}
+
+static TableGen::Emitter::Opt Y("gen-intrinsic-impl", EmitIntrinsicImpl,
+ "Generate intrinsic information");
diff --git a/llvm/utils/TableGen/OptParserEmitter.cpp b/llvm/utils/TableGen/OptParserEmitter.cpp
index 01da32e5e7ea..514346c843d1 100644
--- a/llvm/utils/TableGen/OptParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptParserEmitter.cpp
@@ -7,7 +7,6 @@
//===----------------------------------------------------------------------===//
#include "OptEmitter.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/Twine.h"
@@ -213,8 +212,7 @@ static MarshallingInfo createMarshallingInfo(const Record &R) {
/// OptParserEmitter - This tablegen backend takes an input .td file
/// describing a list of options and emits a data structure for parsing and
/// working with those options when given an input command line.
-namespace llvm {
-void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
// Get the option groups and options.
const std::vector<Record*> &Groups =
Records.getAllDerivedDefinitions("OptionGroup");
@@ -500,4 +498,6 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
OS << "\n";
}
-} // end namespace llvm
+
+static TableGen::Emitter::Opt X("gen-opt-parser-defs", EmitOptParser,
+ "Generate option definitions");
diff --git a/llvm/utils/TableGen/OptRSTEmitter.cpp b/llvm/utils/TableGen/OptRSTEmitter.cpp
index d32522c00f45..87e755d943a1 100644
--- a/llvm/utils/TableGen/OptRSTEmitter.cpp
+++ b/llvm/utils/TableGen/OptRSTEmitter.cpp
@@ -7,17 +7,16 @@
//===----------------------------------------------------------------------===//
#include "OptEmitter.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
/// OptParserEmitter - This tablegen backend takes an input .td file
/// describing a list of options and emits a RST man page.
-namespace llvm {
-void EmitOptRST(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitOptRST(RecordKeeper &Records, raw_ostream &OS) {
llvm::StringMap<std::vector<Record *>> OptionsByGroup;
std::vector<Record *> OptionsWithoutGroup;
@@ -103,4 +102,6 @@ void EmitOptRST(RecordKeeper &Records, raw_ostream &OS) {
}
}
}
-} // end namespace llvm
+
+static TableGen::Emitter::Opt X("gen-opt-rst", EmitOptRST,
+ "Generate option RST");
diff --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
index 75a64f243005..e07fb9188098 100644
--- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -8,7 +8,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
@@ -314,10 +313,5 @@ void PseudoLoweringEmitter::run(raw_ostream &o) {
emitLoweringEmitter(o);
}
-namespace llvm {
-
-void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
- PseudoLoweringEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<PseudoLoweringEmitter>
+ X("gen-pseudo-lowering", "Generate pseudo instruction lowering");
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index b534ce4b3b78..b02f7bd4198e 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -11,9 +11,9 @@
//
//===----------------------------------------------------------------------===//
-#include "TableGenBackends.h"
#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
@@ -47,7 +47,7 @@ static std::string getMArch(const Record &Rec) {
return (*ISAInfo)->toString();
}
-void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
<< "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
<< "#endif\n\n";
@@ -80,3 +80,6 @@ void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "\n#undef TUNE_PROC\n";
}
+
+static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
+ "Generate the list of CPU for RISCV");
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index a5acb50b5d6d..c5ba6a897c77 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -14,7 +14,6 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/TableGen/Error.h"
@@ -328,10 +327,5 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
}
-namespace llvm {
-
-void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS) {
- RegisterBankEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<RegisterBankEmitter>
+ X("gen-register-bank", "Generate registers bank descriptions");
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index aa9a979c6344..0c32a6aa51cc 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -17,7 +17,6 @@
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
#include "SequenceToOffsetTable.h"
-#include "TableGenBackends.h"
#include "Types.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
@@ -1909,10 +1908,5 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
}
}
-namespace llvm {
-
-void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
- RegisterInfoEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<RegisterInfoEmitter>
+ X("gen-register-info", "Generate registers and register classes info");
diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp
index fd6508ceec6f..2fc291708db7 100644
--- a/llvm/utils/TableGen/SearchableTableEmitter.cpp
+++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp
@@ -13,13 +13,13 @@
//===----------------------------------------------------------------------===//
#include "CodeGenIntrinsics.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
#include <set>
#include <string>
@@ -823,10 +823,5 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
OS << "#undef " << Guard << "\n";
}
-namespace llvm {
-
-void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS) {
- SearchableTableEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<SearchableTableEmitter>
+ X("gen-searchable-tables", "Generate generic binary-searchable table");
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 3ff25413b873..9bbf7cd673a0 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -14,7 +14,6 @@
#include "CodeGenSchedule.h"
#include "CodeGenTarget.h"
#include "PredicateExpander.h"
-#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/StringExtras.h"
@@ -1985,10 +1984,5 @@ void SubtargetEmitter::run(raw_ostream &OS) {
EmitMCInstrAnalysisPredicateFunctions(OS);
}
-namespace llvm {
-
-void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
- SubtargetEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<SubtargetEmitter>
+ X("gen-subtarget", "Generate subtarget enumerations");
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index 2ec3deb8ae25..b2ed48cffe6b 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -10,61 +10,20 @@
//
//===----------------------------------------------------------------------===//
-#include "TableGenBackends.h" // Declares all backends.
+#include "llvm/ADT/StringRef.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/InitLLVM.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Main.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/SetTheory.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <cassert>
#include <string>
#include <vector>
using namespace llvm;
-enum ActionType {
- PrintRecords,
- PrintDetailedRecords,
- NullBackend,
- DumpJSON,
- GenEmitter,
- GenRegisterInfo,
- GenInstrInfo,
- GenInstrDocs,
- GenAsmWriter,
- GenAsmMatcher,
- GenDisassembler,
- GenPseudoLowering,
- GenCompressInst,
- GenCallingConv,
- GenDAGISel,
- GenDFAPacketizer,
- GenFastISel,
- GenSubtarget,
- GenIntrinsicEnums,
- GenIntrinsicImpl,
- PrintEnums,
- PrintSets,
- GenOptParserDefs,
- GenOptRST,
- GenCTags,
- GenAttributes,
- GenSearchableTables,
- GenGlobalISel,
- GenGICombiner,
- GenX86EVEX2VEXTables,
- GenX86FoldTables,
- GenX86MnemonicTables,
- GenRegisterBank,
- GenExegesis,
- GenAutomata,
- GenDirectivesEnumDecl,
- GenDirectivesEnumImpl,
- GenDXILOperation,
- GenRISCVTargetDef,
-};
-
namespace llvm {
cl::opt<bool> EmitLongStrLiterals(
"long-string-literals",
@@ -75,227 +34,54 @@ cl::opt<bool> EmitLongStrLiterals(
} // end namespace llvm
namespace {
-cl::opt<ActionType> Action(
- cl::desc("Action to perform:"),
- cl::values(
- clEnumValN(PrintRecords, "print-records",
- "Print all records to stdout (default)"),
- clEnumValN(PrintDetailedRecords, "print-detailed-records",
- "Print full details of all records to stdout"),
- clEnumValN(NullBackend, "null-backend",
- "Do nothing after parsing (useful for timing)"),
- clEnumValN(DumpJSON, "dump-json",
- "Dump all records as machine-readable JSON"),
- clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
- clEnumValN(GenRegisterInfo, "gen-register-info",
- "Generate registers and register classes info"),
- clEnumValN(GenInstrInfo, "gen-instr-info",
- "Generate instruction descriptions"),
- clEnumValN(GenInstrDocs, "gen-instr-docs",
- "Generate instruction documentation"),
- clEnumValN(GenCallingConv, "gen-callingconv",
- "Generate calling convention descriptions"),
- clEnumValN(GenAsmWriter, "gen-asm-writer", "Generate assembly writer"),
- clEnumValN(GenDisassembler, "gen-disassembler",
- "Generate disassembler"),
- clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
- "Generate pseudo instruction lowering"),
- clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
- "Generate RISCV compressed instructions."),
- clEnumValN(GenAsmMatcher, "gen-asm-matcher",
- "Generate assembly instruction matcher"),
- clEnumValN(GenDAGISel, "gen-dag-isel",
- "Generate a DAG instruction selector"),
- clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
- "Generate DFA Packetizer for VLIW targets"),
- clEnumValN(GenFastISel, "gen-fast-isel",
- "Generate a \"fast\" instruction selector"),
- clEnumValN(GenSubtarget, "gen-subtarget",
- "Generate subtarget enumerations"),
- clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums",
- "Generate intrinsic enums"),
- clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl",
- "Generate intrinsic information"),
- clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"),
- clEnumValN(PrintSets, "print-sets",
- "Print expanded sets for testing DAG exprs"),
- clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
- "Generate option definitions"),
- clEnumValN(GenOptRST, "gen-opt-rst", "Generate option RST"),
- clEnumValN(GenCTags, "gen-ctags", "Generate ctags-compatible index"),
- clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"),
- clEnumValN(GenSearchableTables, "gen-searchable-tables",
- "Generate generic binary-searchable table"),
- clEnumValN(GenGlobalISel, "gen-global-isel",
- "Generate GlobalISel selector"),
- clEnumValN(GenGICombiner, "gen-global-isel-combiner",
- "Generate GlobalISel combiner"),
- clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
- "Generate X86 EVEX to VEX compress tables"),
- clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",
- "Generate X86 fold tables"),
- clEnumValN(GenX86MnemonicTables, "gen-x86-mnemonic-tables",
- "Generate X86 mnemonic tables"),
- clEnumValN(GenRegisterBank, "gen-register-bank",
- "Generate registers bank descriptions"),
- clEnumValN(GenExegesis, "gen-exegesis",
- "Generate llvm-exegesis tables"),
- clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
- clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
- "Generate directive related declaration code (header file)"),
- clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
- "Generate directive related implementation code"),
- clEnumValN(GenDXILOperation, "gen-dxil-operation",
- "Generate DXIL operation information"),
- clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
- "Generate the list of CPU for RISCV")));
+
cl::OptionCategory PrintEnumsCat("Options for -print-enums");
cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
cl::value_desc("class name"),
cl::cat(PrintEnumsCat));
-bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
- switch (Action) {
- case PrintRecords:
- OS << Records; // No argument, dump all contents
- break;
- case PrintDetailedRecords:
- EmitDetailedRecords(Records, OS);
- break;
- case NullBackend: // No backend at all.
- break;
- case DumpJSON:
- EmitJSON(Records, OS);
- break;
- case GenEmitter:
- EmitCodeEmitter(Records, OS);
- break;
- case GenRegisterInfo:
- EmitRegisterInfo(Records, OS);
- break;
- case GenInstrInfo:
- EmitInstrInfo(Records, OS);
- break;
- case GenInstrDocs:
- EmitInstrDocs(Records, OS);
- break;
- case GenCallingConv:
- EmitCallingConv(Records, OS);
- break;
- case GenAsmWriter:
- EmitAsmWriter(Records, OS);
- break;
- case GenAsmMatcher:
- EmitAsmMatcher(Records, OS);
- break;
- case GenDisassembler:
- EmitDisassembler(Records, OS);
- break;
- case GenPseudoLowering:
- EmitPseudoLowering(Records, OS);
- break;
- case GenCompressInst:
- EmitCompressInst(Records, OS);
- break;
- case GenDAGISel:
- EmitDAGISel(Records, OS);
- break;
- case GenDFAPacketizer:
- EmitDFAPacketizer(Records, OS);
- break;
- case GenFastISel:
- EmitFastISel(Records, OS);
- break;
- case GenSubtarget:
- EmitSubtarget(Records, OS);
- break;
- case GenIntrinsicEnums:
- EmitIntrinsicEnums(Records, OS);
- break;
- case GenIntrinsicImpl:
- EmitIntrinsicImpl(Records, OS);
- break;
- case GenOptParserDefs:
- EmitOptParser(Records, OS);
- break;
- case GenOptRST:
- EmitOptRST(Records, OS);
- break;
- case PrintEnums: {
- for (Record *Rec : Records.getAllDerivedDefinitions(Class))
- OS << Rec->getName() << ", ";
- OS << "\n";
- break;
- }
- case PrintSets: {
- SetTheory Sets;
- Sets.addFieldExpander("Set", "Elements");
- for (Record *Rec : Records.getAllDerivedDefinitions("Set")) {
- OS << Rec->getName() << " = [";
- const std::vector<Record *> *Elts = Sets.expand(Rec);
- assert(Elts && "Couldn't expand Set instance");
- for (Record *Elt : *Elts)
- OS << ' ' << Elt->getName();
- OS << " ]\n";
- }
- break;
- }
- case GenCTags:
- EmitCTags(Records, OS);
- break;
- case GenAttributes:
- EmitAttributes(Records, OS);
- break;
- case GenSearchableTables:
- EmitSearchableTables(Records, OS);
- break;
- case GenGlobalISel:
- EmitGlobalISel(Records, OS);
- break;
- case GenGICombiner:
- EmitGICombiner(Records, OS);
- break;
- case GenRegisterBank:
- EmitRegisterBank(Records, OS);
- break;
- case GenX86EVEX2VEXTables:
- EmitX86EVEX2VEXTables(Records, OS);
- break;
- case GenX86MnemonicTables:
- EmitX86MnemonicTables(Records, OS);
- break;
- case GenX86FoldTables:
- EmitX86FoldTables(Records, OS);
- break;
- case GenExegesis:
- EmitExegesis(Records, OS);
- break;
- case GenAutomata:
- EmitAutomata(Records, OS);
- break;
- case GenDirectivesEnumDecl:
- EmitDirectivesDecl(Records, OS);
- break;
- case GenDirectivesEnumImpl:
- EmitDirectivesImpl(Records, OS);
- break;
- case GenDXILOperation:
- EmitDXILOperation(Records, OS);
- break;
- case GenRISCVTargetDef:
- EmitRISCVTargetDef(Records, OS);
- break;
- }
+void PrintRecords(RecordKeeper &Records, raw_ostream &OS) {
+ OS << Records; // No argument, dump all contents
+}
- return false;
+void PrintEnums(RecordKeeper &Records, raw_ostream &OS) {
+ for (Record *Rec : Records.getAllDerivedDefinitions(Class))
+ OS << Rec->getName() << ", ";
+ OS << "\n";
}
+
+void PrintSets(RecordKeeper &Records, raw_ostream &OS) {
+ SetTheory Sets;
+ Sets.addFieldExpander("Set", "Elements");
+ for (Record *Rec : Records.getAllDerivedDefinitions("Set")) {
+ OS << Rec->getName() << " = [";
+ const std::vector<Record *> *Elts = Sets.expand(Rec);
+ assert(Elts && "Couldn't expand Set instance");
+ for (Record *Elt : *Elts)
+ OS << ' ' << Elt->getName();
+ OS << " ]\n";
+ }
+}
+
+TableGen::Emitter::Opt X[] = {
+ {"print-records", PrintRecords, "Print all records to stdout (default)",
+ true},
+ {"print-detailed-records", EmitDetailedRecords,
+ "Print full details of all records to stdout"},
+ {"null-backend", [](RecordKeeper &Records, raw_ostream &OS) {},
+ "Do nothing after parsing (useful for timing)"},
+ {"dump-json", EmitJSON, "Dump all records as machine-readable JSON"},
+ {"print-enums", PrintEnums, "Print enum values for a class"},
+ {"print-sets", PrintSets, "Print expanded sets for testing DAG exprs"},
+};
+
} // namespace
int main(int argc, char **argv) {
InitLLVM X(argc, argv);
cl::ParseCommandLineOptions(argc, argv);
- return TableGenMain(argv[0], &LLVMTableGenMain);
+ return TableGenMain(argv[0]);
}
#ifndef __has_feature
diff --git a/llvm/utils/TableGen/TableGenBackends.h b/llvm/utils/TableGen/TableGenBackends.h
index 7be83af3734f..3afe6b01467b 100644
--- a/llvm/utils/TableGen/TableGenBackends.h
+++ b/llvm/utils/TableGen/TableGenBackends.h
@@ -63,40 +63,7 @@ namespace llvm {
class raw_ostream;
class RecordKeeper;
-void EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS);
-void EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS);
-void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS);
-void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS);
-void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS);
-void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS);
-void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS);
-void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS);
-void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS);
-void EmitFastISel(RecordKeeper &RK, raw_ostream &OS);
-void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS);
-void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS);
-void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
-void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS);
-void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS);
-void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS);
void EmitMapTable(RecordKeeper &RK, raw_ostream &OS);
-void EmitOptParser(RecordKeeper &RK, raw_ostream &OS);
-void EmitOptRST(RecordKeeper &RK, raw_ostream &OS);
-void EmitCTags(RecordKeeper &RK, raw_ostream &OS);
-void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);
-void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);
-void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS);
-void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
-void EmitExegesis(RecordKeeper &RK, raw_ostream &OS);
-void EmitAutomata(RecordKeeper &RK, raw_ostream &OS);
-void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
-void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
-void EmitDXILOperation(RecordKeeper &RK, raw_ostream &OS);
-void EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS);
// Defined in DecoderEmitter.cpp
void EmitDecoder(RecordKeeper &RK, raw_ostream &OS,
diff --git a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
index 9a21ccb93729..c0b019534c66 100644
--- a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
@@ -13,7 +13,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "X86RecognizableInstr.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
@@ -241,8 +240,5 @@ void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
}
} // namespace
-namespace llvm {
-void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
- X86EVEX2VEXTablesEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<X86EVEX2VEXTablesEmitter>
+ X("gen-x86-EVEX2VEX-tables", "Generate X86 EVEX to VEX compress tables");
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index e8555df7ba02..864f402fe839 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -13,7 +13,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "X86RecognizableInstr.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/Support/FormattedStream.h"
@@ -614,9 +613,5 @@ void X86FoldTablesEmitter::run(raw_ostream &o) {
printTable(Table4, "Table4", OS);
}
-namespace llvm {
-
-void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS) {
- X86FoldTablesEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<X86FoldTablesEmitter>
+ X("gen-x86-fold-tables", "Generate X86 fold tables");
diff --git a/llvm/utils/TableGen/X86MnemonicTables.cpp b/llvm/utils/TableGen/X86MnemonicTables.cpp
index aca311be6357..aeafee157462 100644
--- a/llvm/utils/TableGen/X86MnemonicTables.cpp
+++ b/llvm/utils/TableGen/X86MnemonicTables.cpp
@@ -13,7 +13,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
-#include "TableGenBackends.h"
#include "X86RecognizableInstr.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -88,8 +87,5 @@ void X86MnemonicTablesEmitter::run(raw_ostream &OS) {
} // namespace
-namespace llvm {
-void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS) {
- X86MnemonicTablesEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<X86MnemonicTablesEmitter>
+ X("gen-x86-mnemonic-tables", "Generate X86 mnemonic tables");
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