[PATCH] D146435: [RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh

[Alex Bradbury via Phabricator via llvm-commits]

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These were previously in a `Predicates = [HasStdExtZfhOrZfhmin]` block, but Zfhmin has no fcmp instructions so the definition makes no sense for Zfhmin.

@craig.topper pretty sure this is just a merging / copy and paste issue based on similar logic on F and D, but thought I'd quickly double check I've not missed something here.


https://reviews.llvm.org/D146435

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -206,15 +206,16 @@
                 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 def : InstAlias<"fge.h $rd, $rs, $rt",
                 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
-} // Predicates = [HasStdExtZfh]
 
-let Predicates = [HasStdExtZfhOrZfhmin] in {
-def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
-def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 let usesCustomInserter = 1 in {
 def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>;
 def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
 }
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZfhOrZfhmin] in {
+def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
+def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 } // Predicates = [HasStdExtZfhOrZfhmin]
 
 let Predicates = [HasStdExtZhinx] in {


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