[PATCH] D139732: [AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin marked 2 inline comments as done.
vpykhtin added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:154-155
+
+unsigned GCNRewritePartialRegUses::getSubReg(unsigned Offset,
+                                             unsigned Size) const {
+  auto R = SubRegs.try_emplace({Offset, Size}, 0);
----------------
arsenm wrote:
> Feels like tablegen should generate something like this which does a binary search of subregister indices
Agree, but there's not much of them used and all of them get cached, so I think we can leave this improvement for later.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.h:423-426
+    assert(AlignNumBits != 0);
+    unsigned RCAlign = getRegClassAlignmentNumBits(RC);
+    return RCAlign == AlignNumBits ||
+           (RCAlign > AlignNumBits && (RCAlign % AlignNumBits) == 0);
----------------
arsenm wrote:
> This should be implied by subregister support. Can you check getSubClassWithSubReg/getMatchingSuperRegClass?
I'm not sure: I need alignment information to prevent rewriting cases like:

```
undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
```
%0.sub0 cannot be rewritten with ordinary VGPR32 as it loses alignment.


Repository:
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  https://reviews.llvm.org/D139732/new/

https://reviews.llvm.org/D139732