[PATCH] D146362: [SelectionDAG][RISCV] Fix SimplifyDemandedBits for scalable vectors

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw created this revision.
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The function `SimplifyDemandedBits` attempts to get the bit-width of a scalable vector type while compiling the `LLVM-test-suite` with `-march=rv64gcv`. This patch skips some simplifications since we assume we know nothing about scalable vectors for now. I am uncertain about how to provide test cases and need some guidance.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146362

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1722,6 +1722,8 @@
         if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
             isTypeDesirableForOp(ISD::SHL, InnerVT)) {
           EVT ShTy = getShiftAmountTy(InnerVT, DL);
+          if (ShTy.isScalableVector())
+            return false;
           if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
             ShTy = InnerVT;
           SDValue NarrowShl =


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