[llvm] 0a895c3 - [RISCV] Add isAsCheapAsAMove to FLI instructions.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-17T12:16:14-07:00
New Revision: 0a895c39adaf35f3c8d29573eb636b2cccf08d7c

URL: https://github.com/llvm/llvm-project/commit/0a895c39adaf35f3c8d29573eb636b2cccf08d7c
DIFF: https://github.com/llvm/llvm-project/commit/0a895c39adaf35f3c8d29573eb636b2cccf08d7c.diff

LOG: [RISCV] Add isAsCheapAsAMove to FLI instructions.

This can prevent unnecessarily hoisting out of loops.

Test case cribbed from AArch64.

I also intend to make them rematerializable.

Differential Revision: https://reviews.llvm.org/D146314

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    llvm/test/CodeGen/RISCV/fli-licm.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index bac642218fe2b..03f2292a571e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -93,6 +93,7 @@ class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfa] in {
+let isAsCheapAsAMove = 1 in
 def FLI_S : FPUnaryOp_imm<0b1111000, 0b00001, 0b000, OPC_OP_FP, (outs FPR32:$rd),
             (ins loadfp32imm:$imm), "fli.s", "$rd, $imm">;
 
@@ -107,6 +108,7 @@ def FLEQ_S : FPCmp_rr<0b1010000, 0b100, "fleq.s", FPR32>;
 } // Predicates = [HasStdExtZfa]
 
 let Predicates = [HasStdExtZfa, HasStdExtD] in {
+let isAsCheapAsAMove = 1 in
 def FLI_D : FPUnaryOp_imm<0b1111001, 0b00001, 0b000, OPC_OP_FP, (outs FPR64:$rd),
             (ins loadfp64imm:$imm), "fli.d", "$rd, $imm">;
 
@@ -136,6 +138,7 @@ def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64,
 } // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
 
 let Predicates = [HasStdExtZfa, HasStdExtZfhOrZvfh] in
+let isAsCheapAsAMove = 1 in
 def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, OPC_OP_FP, (outs FPR16:$rd),
             (ins loadfp16imm:$imm), "fli.h", "$rd, $imm">;
 

diff  --git a/llvm/test/CodeGen/RISCV/fli-licm.ll b/llvm/test/CodeGen/RISCV/fli-licm.ll
index 6ed8823c98ae3..93bb934c1cb0d 100644
--- a/llvm/test/CodeGen/RISCV/fli-licm.ll
+++ b/llvm/test/CodeGen/RISCV/fli-licm.ll
@@ -15,14 +15,12 @@ define void @process_nodes(ptr %0) nounwind {
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    beqz a0, .LBB0_3
 ; RV32-NEXT:  # %bb.1: # %loop.preheader
 ; RV32-NEXT:    mv s0, a0
-; RV32-NEXT:    fli.s fs0, 1.0
 ; RV32-NEXT:  .LBB0_2: # %loop
 ; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32-NEXT:    fmv.s fa0, fs0
+; RV32-NEXT:    fli.s fa0, 1.0
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    call do_it at plt
 ; RV32-NEXT:    lw s0, 0(s0)
@@ -30,32 +28,28 @@ define void @process_nodes(ptr %0) nounwind {
 ; RV32-NEXT:  .LBB0_3: # %exit
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: process_nodes:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    addi sp, sp, -32
-; RV64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; RV64-NEXT:    addi sp, sp, -16
+; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    beqz a0, .LBB0_3
 ; RV64-NEXT:  # %bb.1: # %loop.preheader
 ; RV64-NEXT:    mv s0, a0
-; RV64-NEXT:    fli.s fs0, 1.0
 ; RV64-NEXT:  .LBB0_2: # %loop
 ; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64-NEXT:    fmv.s fa0, fs0
+; RV64-NEXT:    fli.s fa0, 1.0
 ; RV64-NEXT:    mv a0, s0
 ; RV64-NEXT:    call do_it at plt
 ; RV64-NEXT:    ld s0, 0(s0)
 ; RV64-NEXT:    bnez s0, .LBB0_2
 ; RV64-NEXT:  .LBB0_3: # %exit
-; RV64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
-; RV64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
-; RV64-NEXT:    addi sp, sp, 32
+; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 entry:
   %1 = icmp eq ptr %0, null