[PATCH] D146311: [AArch64] Add asm aliases for MOV, LDR, STR with predicate-as-counter

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
Herald added subscribers: jeroen.dobbelaere, hiraditya, kristof.beyls.
Herald added a project: All.
CarolineConcatto requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

In the 2022-12 release of the A64 ISA it was updated that the assembler must
also accept predicate-as-counter register names for the source predicate
register and the destination predicate register for:

- *MOV: Move predicate (unpredicated)*
- *LDR (predicate): Load predicate register*
- *STR (predicate): Store predicate register*


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146311

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/MC/AArch64/SVE/ldr.s
  llvm/test/MC/AArch64/SVE/orr.s
  llvm/test/MC/AArch64/SVE/str.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D146311.506137.patch
Type: text/x-patch
Size: 4021 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230317/de915dcd/attachment.bin>