[PATCH] D146287: [AMDGPU][GISel] Add inverse ballot intrinsic

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:1380
+
+  for (unsigned i = 0; i < NumParts; ++i) {
+    Register DstPart = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
----------------
Emitting the readfirstlanes directly during instruction selection is pretty unusual. Usually it is done by legalizeOperands during SIFixSGPRCopies. Is there a reason that inverse ballot has to be done differently?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146287/new/

https://reviews.llvm.org/D146287