[PATCH] D146303: [llvm-exegesis] Prevent llvm-exegesis from using unsupported opcodes

[Pavel Kosov via Phabricator via llvm-commits]

kpdev42 created this revision.
kpdev42 added reviewers: tstellar, courbet, lebedev.ri.
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When generating snippets for AArch64 with --opcode-index=-1, the code
generator asserts on opcodes that are not supported according to CPU
features.

The same assertion can be triggered even when generating a serial
snippet for a supported opcode if SERIAL_VIA_NON_MEMORY_INSTR execution
mode is used and an unsupported instruction is chosen as the "other
instruction". Unlike the first case, this one may result in flaky
failures because the other instruction is randomly chosen from the
instructions suitable for serializing execution.

This patch adjusts TableGen emitter for *GenInstrInfo.inc to make
possible to query for opcode availability instead of just asserting on
unsupported ones.

~~

Huawei RRI, OS Lab


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146303

Files:
  llvm/include/llvm/MC/MCInstrInfo.h
  llvm/tools/llvm-exegesis/lib/LlvmState.h
  llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
  llvm/tools/llvm-exegesis/llvm-exegesis.cpp
  llvm/utils/TableGen/InstrInfoEmitter.cpp

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