[llvm] 3e12cc9 - [AMDGPU] Simplify AGPR reservation. NFC.

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2023-03-16T16:16:10-07:00
New Revision: 3e12cc9463e6c75212c513e3667be0e334e765ac

URL: https://github.com/llvm/llvm-project/commit/3e12cc9463e6c75212c513e3667be0e334e765ac
DIFF: https://github.com/llvm/llvm-project/commit/3e12cc9463e6c75212c513e3667be0e334e765ac.diff

LOG: [AMDGPU] Simplify AGPR reservation. NFC.

The intent of the code was to reserve all AGPRs on a target without
AGPRs, so just do exactly that. Existing code was unsound.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index f7ce581f97363..3bb93b72c3473 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -654,8 +654,7 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   // Reserve all the AGPRs if there are no instructions to use it.
   if (!ST.hasMAIInsts()) {
-    for (unsigned i = 0; i < MaxNumAGPRs; ++i) {
-      unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
+    for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
       reserveRegisterTuples(Reserved, Reg);
     }
   }