[PATCH] D146212: [AArch64] Use NEON's tbl1 for 16xi8 build vector with mask.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10218
+  // TBL1.
+  if (VT.getSimpleVT() != MVT::v16i8)
+    return SDValue();
----------------
Why limit this it v16i8?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10219
+  if (VT.getSimpleVT() != MVT::v16i8)
+    return SDValue();
+
----------------
It looks like we are missing test coverage for most (all?) exits. It would be great if you could extend the test coverage.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146212/new/

https://reviews.llvm.org/D146212