[llvm] 185ea86 - [RISCV] Fix missing addi in test to validate lower inline asm m with offset

[Mikhail R. Gadelha via llvm-commits]

Author: Mikhail R. Gadelha
Date: 2023-03-16T13:30:53-03:00
New Revision: 185ea867eb145905cbfaf1d57fe6ecb959805d84

URL: https://github.com/llvm/llvm-project/commit/185ea867eb145905cbfaf1d57fe6ecb959805d84
DIFF: https://github.com/llvm/llvm-project/commit/185ea867eb145905cbfaf1d57fe6ecb959805d84.diff

LOG: [RISCV] Fix missing addi in test to validate lower inline asm m with offset

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/inline-asm.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
index ba78d722a16d..22d382517ccd 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -93,6 +93,8 @@ define i32 @constraint_m_with_offset(ptr %a) nounwind {
 ;
 ; RV64I-LABEL: constraint_m_with_offset:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 4
+; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret