[llvm] 7d10b47 - [RISCV][MC][NFC] Refactor RISCVAsmPrinter::PrintAsmMemoryOperand to use early return
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 16 08:05:13 PDT 2023
Author: Alex Bradbury
Date: 2023-03-16T15:02:53Z
New Revision: 7d10b4745054bd8141293e66b74bcd694fc8ef9d
URL: https://github.com/llvm/llvm-project/commit/7d10b4745054bd8141293e66b74bcd694fc8ef9d
DIFF: https://github.com/llvm/llvm-project/commit/7d10b4745054bd8141293e66b74bcd694fc8ef9d.diff
LOG: [RISCV][MC][NFC] Refactor RISCVAsmPrinter::PrintAsmMemoryOperand to use early return
Added:
Modified:
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 30a26e404cbbe..6eefaa27539b3 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -178,18 +178,17 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNo,
const char *ExtraCode,
raw_ostream &OS) {
- if (!ExtraCode) {
- const MachineOperand &MO = MI->getOperand(OpNo);
- // For now, we only support register memory operands in registers and
- // assume there is no addend
- if (!MO.isReg())
- return true;
-
- OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
- return false;
- }
+ if (ExtraCode)
+ return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
- return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ // For now, we only support register memory operands in registers and
+ // assume there is no addend
+ if (!MO.isReg())
+ return true;
+
+ OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
+ return false;
}
bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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