[PATCH] D146121: [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits (WIP)
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 16 03:20:22 PDT 2023
RKSimon added inline comments.
================
Comment at: llvm/test/CodeGen/X86/h-register-addressing-64.ll:67
+; CHECK-NEXT: andl $2040, %esi # imm = 0x7F8
+; CHECK-NEXT: movzbl (%rdi,%rsi), %eax
; CHECK-NEXT: retq
----------------
kazu wrote:
> goldstein.w.n wrote:
> > I think this is okay here. We only get the right codegen by chance here and I don't think its something we can reasonably control during DAG isel.
> >
> > I tried to improve this with D141653. Looked good for the tests but caused infinite loop in bootstrap build.
> >
> > I think this (along with other `imm` level optimizations), need to be moved to a new pass (or function in isel) that runs at the very end.
> > > think this (along with other `imm` level optimizations), need to be moved to a new pass (or function in isel) that runs at the very end.
>
> I was just thinking about something similar. Specifically, optimizations to achieve smaller encoding with the same opcode should move to a new pass. Otherwise, we would have to see through `ISD::ZERO_EXTEND` and `ISD::TRUNCATE` everywhere, and that would be prone to missed optimizations.
>
> Do we have known bits and demanded bits infrastructure at the x86 MIR level? (I'm guessing not.) Also, I am wondering whether a new pass would be more effective if we use information across basic blocks.
Adding value tracking at that level would be a huge amount of work - both X86 and AMDGPU currently using the DAG narrowing code, but ideally we'd be working to enable it on other targets as well.
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https://reviews.llvm.org/D146121/new/
https://reviews.llvm.org/D146121
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