[PATCH] D145155: [RISCV] Enable interleaved access vectorization

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll:11
+; VF_2-LABEL: Checking a loop in 'i8_factor_2'
+; VF_2:       Found an estimated cost of 3 for VF 2 For instruction:   %l0 = load i8, ptr %p0, align 1
+; VF_2-NEXT:  Found an estimated cost of 0 for VF 2 For instruction:   %l1 = load i8, ptr %p1, align 1
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@reames Apologies for jumping the gun there, this is the line that fails without that change to `getShuffleCost`.

I've split it out into D146176, but the gist is that this deinterleaved load ends up getting costed as an interleave because it has a mask of `<0, 2>`

This test case covers it but I wasn't able to find a way to test it in the aforementioned patch due to how getInstructionCost doesn't cost shuffles that change length. (Happy to take a look into that though if needed)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145155/new/

https://reviews.llvm.org/D145155