[PATCH] D142746: AMDGPU: Fold fneg into bitcast of build_vector
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 15:28:56 PDT 2023
arsenm added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:4144-4145
+ // fneg (f64 (bitcast (build_vector x, y))) ->
+ // f64 (bitcast (build_vector (bitcast i32:x to f32),
+ // (fneg (bitcast i32:y to f32)))
+
----------------
Pierre-vh wrote:
> Wouldn't it make more sense to bitcast the fneg back to i32 to get 2xi32 -> f64? Would that change codegen?
> 2xf32 -> f64 looks wrong to me (even though it's correct in that context)
That would just introduce new bitcasts, which would be equally foldable back. Minimal bitcasts is better. They get in the way enough as is
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:4139-4153
+ SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::f32, HighBits);
+ SDValue NegHi = DAG.getNode(ISD::FNEG, SL, MVT::f32, CastHi);
+ SDValue CastBack =
+ DAG.getNode(ISD::BITCAST, SL, HighBits.getValueType(), NegHi);
+
+ SmallVector<SDValue, 8> Ops(BCSrc->op_begin(), BCSrc->op_end());
+ Ops.back() = CastBack;
----------------
Pierre-vh wrote:
> Can you add a comment to show what this is doing? (`A -> B` style comment like we usually do for DAG combines)
>
That's already what's above?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142746/new/
https://reviews.llvm.org/D142746
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