[llvm] 1def314 - [AArch64] Add hex comments to mov-imm spellings in the InstPrinter
Jon Roelofs via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 14:09:26 PDT 2023
Author: Jon Roelofs
Date: 2023-03-15T14:08:51-07:00
New Revision: 1def3141135c072a1d3e51e82e113dd67b0def97
URL: https://github.com/llvm/llvm-project/commit/1def3141135c072a1d3e51e82e113dd67b0def97
DIFF: https://github.com/llvm/llvm-project/commit/1def3141135c072a1d3e51e82e113dd67b0def97.diff
LOG: [AArch64] Add hex comments to mov-imm spellings in the InstPrinter
Differential Revision: https://reviews.llvm.org/D146105
Added:
Modified:
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/test/CodeGen/AArch64/movw-consts.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 7c32c6f7361f..2983e9a9be92 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -282,6 +282,23 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
return;
}
+ auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
+ int64_t SExtVal = SignExtend64(Value, RegWidth);
+ O << "\tmov\t";
+ printRegName(O, MI->getOperand(0).getReg());
+ O << ", " << markup("<imm:") << "#"
+ << formatImm(SExtVal) << markup(">");
+ if (CommentStream) {
+ // Do the opposite to that used for instruction operands.
+ if (getPrintImmHex())
+ *CommentStream << '=' << formatDec(SExtVal) << '\n';
+ else {
+ uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
+ *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
+ }
+ }
+ };
+
// MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
// domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
// MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
@@ -295,10 +312,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
if (AArch64_AM::isMOVZMovAlias(Value, Shift,
Opcode == AArch64::MOVZXi ? 64 : 32)) {
- O << "\tmov\t";
- printRegName(O, MI->getOperand(0).getReg());
- O << ", " << markup("<imm:") << "#"
- << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+ PrintMovImm(Value, RegWidth);
return;
}
}
@@ -312,10 +326,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
Value = Value & 0xffffffff;
if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
- O << "\tmov\t";
- printRegName(O, MI->getOperand(0).getReg());
- O << ", " << markup("<imm:") << "#"
- << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+ PrintMovImm(Value, RegWidth);
return;
}
}
@@ -328,10 +339,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
uint64_t Value = AArch64_AM::decodeLogicalImmediate(
MI->getOperand(2).getImm(), RegWidth);
if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
- O << "\tmov\t";
- printRegName(O, MI->getOperand(0).getReg());
- O << ", " << markup("<imm:") << "#"
- << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+ PrintMovImm(Value, RegWidth);
return;
}
}
diff --git a/llvm/test/CodeGen/AArch64/movw-consts.ll b/llvm/test/CodeGen/AArch64/movw-consts.ll
index d585f74199cc..a351f0dfcd69 100644
--- a/llvm/test/CodeGen/AArch64/movw-consts.ll
+++ b/llvm/test/CodeGen/AArch64/movw-consts.ll
@@ -13,7 +13,7 @@ define i64 @test0() {
define i64 @test1() {
; CHECK-LABEL: test1:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: mov w0, #1 ; =0x1
; CHECK-NEXT: ret
ret i64 1
}
@@ -21,7 +21,7 @@ define i64 @test1() {
define i64 @test2() {
; CHECK-LABEL: test2:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #65535
+; CHECK-NEXT: mov w0, #65535 ; =0xffff
; CHECK-NEXT: ret
ret i64 65535
}
@@ -29,7 +29,7 @@ define i64 @test2() {
define i64 @test3() {
; CHECK-LABEL: test3:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #65536
+; CHECK-NEXT: mov w0, #65536 ; =0x10000
; CHECK-NEXT: ret
ret i64 65536
}
@@ -37,7 +37,7 @@ define i64 @test3() {
define i64 @test4() {
; CHECK-LABEL: test4:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #-65536
+; CHECK-NEXT: mov w0, #-65536 ; =0xffff0000
; CHECK-NEXT: ret
ret i64 4294901760
}
@@ -45,7 +45,7 @@ define i64 @test4() {
define i64 @test5() {
; CHECK-LABEL: test5:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #4294967296
+; CHECK-NEXT: mov x0, #4294967296 ; =0x100000000
; CHECK-NEXT: ret
ret i64 4294967296
}
@@ -53,7 +53,7 @@ define i64 @test5() {
define i64 @test6() {
; CHECK-LABEL: test6:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #281470681743360
+; CHECK-NEXT: mov x0, #281470681743360 ; =0xffff00000000
; CHECK-NEXT: ret
ret i64 281470681743360
}
@@ -61,7 +61,7 @@ define i64 @test6() {
define i64 @test7() {
; CHECK-LABEL: test7:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #281474976710656
+; CHECK-NEXT: mov x0, #281474976710656 ; =0x1000000000000
; CHECK-NEXT: ret
ret i64 281474976710656
}
@@ -71,7 +71,7 @@ define i64 @test7() {
define i64 @test8() {
; CHECK-LABEL: test8:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #-60876
+; CHECK-NEXT: mov w0, #-60876 ; =0xffff1234
; CHECK-NEXT: ret
ret i64 4294906420
}
@@ -79,7 +79,7 @@ define i64 @test8() {
define i64 @test9() {
; CHECK-LABEL: test9:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #-1
+; CHECK-NEXT: mov x0, #-1 ; =0xffffffffffffffff
; CHECK-NEXT: ret
ret i64 -1
}
@@ -87,7 +87,7 @@ define i64 @test9() {
define i64 @test10() {
; CHECK-LABEL: test10:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #-3989504001
+; CHECK-NEXT: mov x0, #-3989504001 ; =0xffffffff1234ffff
; CHECK-NEXT: ret
ret i64 18446744069720047615
}
@@ -110,7 +110,7 @@ define void @test12() {
; CHECK-LABEL: test12:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32 at PAGE
-; CHECK-NEXT: mov w9, #1
+; CHECK-NEXT: mov w9, #1 ; =0x1
; CHECK-NEXT: str w9, [x8, _var32 at PAGEOFF]
; CHECK-NEXT: ret
store i32 1, ptr @var32
@@ -121,7 +121,7 @@ define void @test13() {
; CHECK-LABEL: test13:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32 at PAGE
-; CHECK-NEXT: mov w9, #65535
+; CHECK-NEXT: mov w9, #65535 ; =0xffff
; CHECK-NEXT: str w9, [x8, _var32 at PAGEOFF]
; CHECK-NEXT: ret
store i32 65535, ptr @var32
@@ -132,7 +132,7 @@ define void @test14() {
; CHECK-LABEL: test14:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32 at PAGE
-; CHECK-NEXT: mov w9, #65536
+; CHECK-NEXT: mov w9, #65536 ; =0x10000
; CHECK-NEXT: str w9, [x8, _var32 at PAGEOFF]
; CHECK-NEXT: ret
store i32 65536, ptr @var32
@@ -143,7 +143,7 @@ define void @test15() {
; CHECK-LABEL: test15:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32 at PAGE
-; CHECK-NEXT: mov w9, #-65536
+; CHECK-NEXT: mov w9, #-65536 ; =0xffff0000
; CHECK-NEXT: str w9, [x8, _var32 at PAGEOFF]
; CHECK-NEXT: ret
store i32 4294901760, ptr @var32
@@ -154,7 +154,7 @@ define void @test16() {
; CHECK-LABEL: test16:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32 at PAGE
-; CHECK-NEXT: mov w9, #-1
+; CHECK-NEXT: mov w9, #-1 ; =0xffffffff
; CHECK-NEXT: str w9, [x8, _var32 at PAGEOFF]
; CHECK-NEXT: ret
store i32 -1, ptr @var32
@@ -164,7 +164,7 @@ define void @test16() {
define i64 @test17() {
; CHECK-LABEL: test17:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #-3
+; CHECK-NEXT: mov x0, #-3 ; =0xfffffffffffffffd
; CHECK-NEXT: ret
; Mustn't MOVN w0 here.
More information about the llvm-commits
mailing list