[PATCH] D144925: [RISCV][NFC] Replace the pseudos for instructions that depend on lmul with variants that encode the SEW into the name

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:114
+    if !eq(mx, "UpperBound") then
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+    else
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michaelmaitland wrote:
> nitinjohnraj wrote:
> > michaelmaitland wrote:
> > > Why don't we make this case SEW aware?
> > Did we want to make UpperBound SEW-aware, or handle it in a different way? IIRC we discussed using it as a defined variable?
> I think the best solution for now is to use the largest LMUL and the largest SEW for that given LMUL as the UpperBound SchedWrite. This assumes that the largest LMUL and SEW has the largest latency and uses the most resource cycles. This assumption may not always true, but I think is a good starting point.
If the worst case is the **number** of elements rather than the size of elements you'd want to use smallest sew.


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https://reviews.llvm.org/D144925