[llvm] 5be5510 - [X86] lzcnt-cmp.ll - enable CMOV on 32-bit LZCNT tests

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-03-15T18:14:53Z
New Revision: 5be551009864b417ec5987294ffc5a2a1d8fa69e

URL: https://github.com/llvm/llvm-project/commit/5be551009864b417ec5987294ffc5a2a1d8fa69e
DIFF: https://github.com/llvm/llvm-project/commit/5be551009864b417ec5987294ffc5a2a1d8fa69e.diff

LOG: [X86] lzcnt-cmp.ll - enable CMOV on 32-bit LZCNT tests

There are no 32-bit targets that have LZCNT but not CMOV, and this allows us to test the straight line i64 pattern - otherwise we're doing the same branchy code as the 32-bit BSR test

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/lzcnt-cmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
index 01d6c0ed483b..b2c1ffd799e3 100644
--- a/llvm/test/CodeGen/X86/lzcnt-cmp.ll
+++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=X86,X86-BSR
-; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt | FileCheck %s --check-prefixes=X86,X86-LZCNT
+; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt,+cmov | FileCheck %s --check-prefixes=X86,X86-LZCNT
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=X64,X64-BSR
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+lzcnt | FileCheck %s --check-prefixes=X64,X64-LZCNT
 
@@ -56,14 +56,12 @@ define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) nounwind {
 ;
 ; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
 ; X86-LZCNT:       # %bb.0:
-; X86-LZCNT-NEXT:    xorl %eax, %eax
-; X86-LZCNT-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X86-LZCNT-NEXT:    jne .LBB1_2
-; X86-LZCNT-NEXT:  # %bb.1:
 ; X86-LZCNT-NEXT:    lzcntl {{[0-9]+}}(%esp), %eax
 ; X86-LZCNT-NEXT:    addl $32, %eax
-; X86-LZCNT-NEXT:  .LBB1_2:
-; X86-LZCNT-NEXT:    testb $64, %al
+; X86-LZCNT-NEXT:    xorl %ecx, %ecx
+; X86-LZCNT-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
+; X86-LZCNT-NEXT:    cmovel %eax, %ecx
+; X86-LZCNT-NEXT:    testb $64, %cl
 ; X86-LZCNT-NEXT:    setne %al
 ; X86-LZCNT-NEXT:    retl
 ;
@@ -139,14 +137,12 @@ define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) nounwind {
 ;
 ; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpne_zero_i64:
 ; X86-LZCNT:       # %bb.0:
-; X86-LZCNT-NEXT:    xorl %eax, %eax
-; X86-LZCNT-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X86-LZCNT-NEXT:    jne .LBB3_2
-; X86-LZCNT-NEXT:  # %bb.1:
 ; X86-LZCNT-NEXT:    lzcntl {{[0-9]+}}(%esp), %eax
 ; X86-LZCNT-NEXT:    addl $32, %eax
-; X86-LZCNT-NEXT:  .LBB3_2:
-; X86-LZCNT-NEXT:    testb $64, %al
+; X86-LZCNT-NEXT:    xorl %ecx, %ecx
+; X86-LZCNT-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
+; X86-LZCNT-NEXT:    cmovel %eax, %ecx
+; X86-LZCNT-NEXT:    testb $64, %cl
 ; X86-LZCNT-NEXT:    setne %al
 ; X86-LZCNT-NEXT:    retl
 ;