[llvm] 28a0d0e - [DAG] Don't fold zext(logicalshift(zext(x),c)) -> logicalshift(zext(x),c) if the outer zext is free

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-03-15T17:45:12Z
New Revision: 28a0d0e85ab5fe9ccc5cd684bd28bfb15f661f45

URL: https://github.com/llvm/llvm-project/commit/28a0d0e85ab5fe9ccc5cd684bd28bfb15f661f45
DIFF: https://github.com/llvm/llvm-project/commit/28a0d0e85ab5fe9ccc5cd684bd28bfb15f661f45.diff

LOG: [DAG] Don't fold zext(logicalshift(zext(x),c)) -> logicalshift(zext(x),c) if the outer zext is free

Avoid widening the shift to a bigger type if the zext would be free anyway

Pulled out of D146121

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/X86/zext-lshr.ll
    llvm/test/CodeGen/X86/zext-shl.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c848847f24f24..7667b38c744ca 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13426,7 +13426,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   }
 
   // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
-  if (N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) {
+  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
+      !TLI.isZExtFree(N0, VT)) {
     SDValue ShVal = N0.getOperand(0);
     SDValue ShAmt = N0.getOperand(1);
     if (auto *ShAmtC = dyn_cast<ConstantSDNode>(ShAmt)) {

diff  --git a/llvm/test/CodeGen/X86/zext-lshr.ll b/llvm/test/CodeGen/X86/zext-lshr.ll
index 3d384c621a2a6..fbfd7b7e1bfe0 100644
--- a/llvm/test/CodeGen/X86/zext-lshr.ll
+++ b/llvm/test/CodeGen/X86/zext-lshr.ll
@@ -61,7 +61,7 @@ define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind {
 ; X64-LABEL: i64_zext_shift_i32_zext_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    shrq $3, %rax
+; X64-NEXT:    shrl $3, %eax
 ; X64-NEXT:    retq
   %t0 = zext i8 %a0 to i32
   %t1 = lshr i32 %t0, 3
@@ -80,7 +80,7 @@ define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind {
 ; X64-LABEL: i64_zext_shift_i32_zext_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzwl %di, %eax
-; X64-NEXT:    shrq $5, %rax
+; X64-NEXT:    shrl $5, %eax
 ; X64-NEXT:    retq
   %t0 = zext i16 %a0 to i32
   %t1 = lshr i32 %t0, 5

diff  --git a/llvm/test/CodeGen/X86/zext-shl.ll b/llvm/test/CodeGen/X86/zext-shl.ll
index 1290b09b01120..8c27e0da6acf7 100644
--- a/llvm/test/CodeGen/X86/zext-shl.ll
+++ b/llvm/test/CodeGen/X86/zext-shl.ll
@@ -70,7 +70,7 @@ define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind {
 ; X64-LABEL: i64_zext_shift_i32_zext_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    shlq $3, %rax
+; X64-NEXT:    shll $3, %eax
 ; X64-NEXT:    retq
   %t0 = zext i8 %a0 to i32
   %t1 = shl i32 %t0, 3
@@ -89,7 +89,7 @@ define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind {
 ; X64-LABEL: i64_zext_shift_i32_zext_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzwl %di, %eax
-; X64-NEXT:    shlq $5, %rax
+; X64-NEXT:    shll $5, %eax
 ; X64-NEXT:    retq
   %t0 = zext i16 %a0 to i32
   %t1 = shl i32 %t0, 5