[llvm] 2281286 - [X86] Add more thorough testing of the zext(logicalshift(zext(x),c)) -> logicalshift(zext(x),c) fold
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 10:20:51 PDT 2023
Author: Simon Pilgrim
Date: 2023-03-15T17:20:42Z
New Revision: 2281286eb7a1b03927dbc18aa9ef242557a36bdf
URL: https://github.com/llvm/llvm-project/commit/2281286eb7a1b03927dbc18aa9ef242557a36bdf
DIFF: https://github.com/llvm/llvm-project/commit/2281286eb7a1b03927dbc18aa9ef242557a36bdf.diff
LOG: [X86] Add more thorough testing of the zext(logicalshift(zext(x),c)) -> logicalshift(zext(x),c) fold
Add tests for more extension combos, 64-bit targets and some illegal types
Added:
llvm/test/CodeGen/X86/zext-lshr.ll
Modified:
llvm/test/CodeGen/X86/zext-shl.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/zext-lshr.ll b/llvm/test/CodeGen/X86/zext-lshr.ll
new file mode 100644
index 000000000000..3d384c621a2a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/zext-lshr.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X64
+
+define i32 @i32_zext_shift_i16_zext_i1(i1 %a0) nounwind {
+; CHECK-LABEL: i32_zext_shift_i16_zext_i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: ret{{[l|q]}}
+ %t0 = zext i1 %a0 to i16
+ %t1 = lshr i16 %t0, 5
+ %t2 = zext i16 %t1 to i32
+ ret i32 %t2
+}
+
+define i32 @i32_zext_shift_i16_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i32_zext_shift_i16_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shrl $5, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: i32_zext_shift_i16_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shrl $5, %eax
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i16
+ %t1 = lshr i16 %t0, 5
+ %t2 = zext i16 %t1 to i32
+ ret i32 %t2
+}
+
+define i64 @i64_zext_shift_i16_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i64_zext_shift_i16_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shrl $5, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LABEL: i64_zext_shift_i16_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shrq $5, %rax
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i16
+ %t1 = lshr i16 %t0, 5
+ %t2 = zext i16 %t1 to i64
+ ret i64 %t2
+}
+
+define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i64_zext_shift_i32_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shrl $3, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LABEL: i64_zext_shift_i32_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shrq $3, %rax
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i32
+ %t1 = lshr i32 %t0, 3
+ %t2 = zext i32 %t1 to i64
+ ret i64 %t2
+}
+
+define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind {
+; X86-LABEL: i64_zext_shift_i32_zext_i16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shrl $5, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LABEL: i64_zext_shift_i32_zext_i16:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: shrq $5, %rax
+; X64-NEXT: retq
+ %t0 = zext i16 %a0 to i32
+ %t1 = lshr i32 %t0, 5
+ %t2 = zext i32 %t1 to i64
+ ret i64 %t2
+}
+
+define i128 @i128_zext_shift_i64_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i128_zext_shift_i64_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shrl $4, %ecx
+; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl $0, 12(%eax)
+; X86-NEXT: movl $0, 8(%eax)
+; X86-NEXT: movl $0, 4(%eax)
+; X86-NEXT: retl $4
+;
+; X64-LABEL: i128_zext_shift_i64_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shrq $4, %rax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i64
+ %t1 = lshr i64 %t0, 4
+ %t2 = zext i64 %t1 to i128
+ ret i128 %t2
+}
+
+define i128 @i128_zext_shift_i64_zext_i16(i16 %a0) nounwind {
+; X86-LABEL: i128_zext_shift_i64_zext_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shrl $7, %ecx
+; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl $0, 12(%eax)
+; X86-NEXT: movl $0, 8(%eax)
+; X86-NEXT: movl $0, 4(%eax)
+; X86-NEXT: retl $4
+;
+; X64-LABEL: i128_zext_shift_i64_zext_i16:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: shrq $7, %rax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: retq
+ %t0 = zext i16 %a0 to i64
+ %t1 = lshr i64 %t0,7
+ %t2 = zext i64 %t1 to i128
+ ret i128 %t2
+}
diff --git a/llvm/test/CodeGen/X86/zext-shl.ll b/llvm/test/CodeGen/X86/zext-shl.ll
index 1b9c813bc1e6..1290b09b0112 100644
--- a/llvm/test/CodeGen/X86/zext-shl.ll
+++ b/llvm/test/CodeGen/X86/zext-shl.ll
@@ -1,26 +1,146 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
-define i32 @t1(i8 zeroext %x) nounwind {
-; CHECK-LABEL: t1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: shll $5, %eax
-; CHECK-NEXT: retl
- %t0 = zext i8 %x to i16
+define i32 @i32_zext_shift_i16_zext_i1(i1 %a0) nounwind {
+; X86-LABEL: i32_zext_shift_i16_zext_i1:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: shll $5, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: i32_zext_shift_i16_zext_i1:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: andl $1, %eax
+; X64-NEXT: shll $5, %eax
+; X64-NEXT: retq
+ %t0 = zext i1 %a0 to i16
%t1 = shl i16 %t0, 5
%t2 = zext i16 %t1 to i32
ret i32 %t2
}
-define i32 @t2(i8 zeroext %x) nounwind {
-; CHECK-LABEL: t2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: shrl $3, %eax
-; CHECK-NEXT: retl
- %t0 = zext i8 %x to i16
- %t1 = lshr i16 %t0, 3
+define i32 @i32_zext_shift_i16_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i32_zext_shift_i16_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shll $5, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: i32_zext_shift_i16_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shll $5, %eax
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i16
+ %t1 = shl i16 %t0, 5
%t2 = zext i16 %t1 to i32
ret i32 %t2
}
+
+define i64 @i64_zext_shift_i16_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i64_zext_shift_i16_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shll $5, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LABEL: i64_zext_shift_i16_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shlq $5, %rax
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i16
+ %t1 = shl i16 %t0, 5
+ %t2 = zext i16 %t1 to i64
+ ret i64 %t2
+}
+
+define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i64_zext_shift_i32_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shll $3, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LABEL: i64_zext_shift_i32_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shlq $3, %rax
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i32
+ %t1 = shl i32 %t0, 3
+ %t2 = zext i32 %t1 to i64
+ ret i64 %t2
+}
+
+define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind {
+; X86-LABEL: i64_zext_shift_i32_zext_i16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shll $5, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LABEL: i64_zext_shift_i32_zext_i16:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: shlq $5, %rax
+; X64-NEXT: retq
+ %t0 = zext i16 %a0 to i32
+ %t1 = shl i32 %t0, 5
+ %t2 = zext i32 %t1 to i64
+ ret i64 %t2
+}
+
+define i128 @i128_zext_shift_i64_zext_i8(i8 %a0) nounwind {
+; X86-LABEL: i128_zext_shift_i64_zext_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shll $4, %ecx
+; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl $0, 12(%eax)
+; X86-NEXT: movl $0, 8(%eax)
+; X86-NEXT: movl $0, 4(%eax)
+; X86-NEXT: retl $4
+;
+; X64-LABEL: i128_zext_shift_i64_zext_i8:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: shlq $4, %rax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: retq
+ %t0 = zext i8 %a0 to i64
+ %t1 = shl i64 %t0, 4
+ %t2 = zext i64 %t1 to i128
+ ret i128 %t2
+}
+
+define i128 @i128_zext_shift_i64_zext_i16(i16 %a0) nounwind {
+; X86-LABEL: i128_zext_shift_i64_zext_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shll $7, %ecx
+; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl $0, 12(%eax)
+; X86-NEXT: movl $0, 8(%eax)
+; X86-NEXT: movl $0, 4(%eax)
+; X86-NEXT: retl $4
+;
+; X64-LABEL: i128_zext_shift_i64_zext_i16:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: shlq $7, %rax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: retq
+ %t0 = zext i16 %a0 to i64
+ %t1 = shl i64 %t0,7
+ %t2 = zext i64 %t1 to i128
+ ret i128 %t2
+}
More information about the llvm-commits
mailing list