[PATCH] D140381: [PowerPC] Use Power9 test data class instruction to lower IS_FPCLASS
Serge Pavlov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 03:48:52 PDT 2023
sepavloff added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11045
+ SDValue Rest = getDataClassTest(Op, Mask & ~fcNormal, Dl, DAG, Subtarget);
+ SDValue Rev{DAG.getMachineNode(
+ TestOp, Dl, MVT::i32,
----------------
According to the LLVM coding stype (https://llvm.org/docs/CodingStandards.html#do-not-use-braced-initializer-lists-to-call-a-constructor) constructor with parentheses should be used. It also applies to some initializations below.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11064
+ MVT::i1)};
+ if (Mask & fcPosNormal)
+ Sign = DAG.getNOT(Dl, Sign, MVT::i1);
----------------
It seems that if `Mask` is `fcNormal` (which is `fcPosNormal | fcNegNormal`), the OR node is not needed.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11074
+ SDValue Rest =
+ getDataClassTest(Op, Mask & (fcAllFlags ^ fcNan), Dl, DAG, Subtarget);
+ bool IsQuiet = Mask & fcQNan;
----------------
`Mask & ~fcNan` should be enough.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140381/new/
https://reviews.llvm.org/D140381
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